[Oberon] [EXT] Project Oberon 2013 on RISC-V

Rikke Solbjørg rikke.solbjorg at gmail.com
Tue Dec 22 01:12:39 CET 2020


We haven't decided what FPGA to target yet, although hopefully our 
options aren't too limited. None of the drivers are changed, and there 
are many open-source RV32IM cores out there that are quite compact, so 
it shouldn't demand much of the FPGA. As an example, darkriscv is a 
simple RV32I implementation in 1000-1500 LUTs: 

For reference, from what I can tell the Spartan-3 board that RISC5 was 
originally implemented for can support a design of ~4000 LUTs. So, I 
can't say for certain, but I believe that shouldn't be much of a 
limitation. Of course, that's without considering SRAM, ports, and so on.

In short, I think most FPGAs that could reasonably run RISC5 Oberon 
before could run this too, but no promises. We're working on it though :)


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