[Oberon] RISK-V RV32IM
joerg.straube at iaeth.ch
Tue Dec 22 13:03:33 CET 2020
BTW: I just recently stumbled over the rather new floating point represenation called „bfloat16“.
It is not part of IEEE 754 standard (yet) but seems to be THE hype lately: 16 bits seem to be enough for machine learning and most graphic applications in game engines and is much faster than 32 bit.
IEEE 754 offers a 16 bit half-precision floating point as well but has a big drawback:
Converting between IEEE single-precision (32 bits) and IEEE half-precision (16 bits) needs HW shifters and comparators.
Converting IEEE single-precision to/from bloat16 is HW-wise much easier.
In case you intend to implement REALs, you might opt for bfloat16.
bloat16 is obviously not a general purpose floating point representation like (IEEE single precision) as its precision is not huge. However, for a lot of applications (AI, games) where REALs are needed, bfloat16 is good enough.
> Am 22.12.2020 um 00:55 schrieb Rikke Solbjørg <rikke.solbjorg at gmail.com>:
> Yes, RV32IM is the compiler's target processor. RV simply means RISC-V, 32 means 32-bit, I is the base instruction set containing fundamental, necessary instructions, and M is a small extension that adds instructions for multiplication and division.
> You could quite easily get floating-point by adding the F extension, or with software emulation. If you add the F extension, you could implement it very similarly to how it is implemented in ORG.Mod. I decided against adding the F extension to the target processor, as it wasn't necessary to get Oberon running, and it would mean having to use a larger core for the FPGA to support it. I might add floating-point emulation, but it's pretty low on my priority list at the moment.
> Also, the rows in the table are good, thank you for adding it! I added the "ø" in my last name; it's not on most keyboards :)
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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