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Hola Pablo<br>
<br>
I use VHDL also, is safer. opp... keep calm I'm not trying to start
the war again.<br>
<br>
I'm working in a VHDL version of RISC5 but as free time project; if
you have some free time you are welcome (
<a class="moz-txt-link-abbreviated" href="mailto:walter@waltergallegos.com">walter@waltergallegos.com</a>) <br>
<br>
Saludos,<br>
Walter<br>
<br>
PD : I like wine.<br>
<br>
<div class="moz-cite-prefix">El 2016-02-16 a las 15:14, Pablo
Cayuela escribió:<br>
</div>
<blockquote
cite="mid:CABM0idyv-O7sj3vJnEC+GtVGXazLt+Rv+=kFRO-nUSKunAFgMA@mail.gmail.com"
type="cite">
<div dir="ltr">
<div>
<div>
<div>As a professor I teach Programmable Logic at
Universidad Tecnologica Nacional, Cordoba, Argentina,
encouraging Synchronous Design for FGPAs.<br>
</div>
It is really useful your suggestions for corrections to the
design of RISC5. I wonder if you or someone else have a VHDL
version of RISC5, because we use VHDL in classes and it
could be useful to use it as an application example. It
could be useful a recipe version of your suggestion for
reimplementing RISC5 in the Verilog version.<br>
</div>
<div>I'm always been considering Wirth's LoLa as a tool but I
could not use it in classes right now. And for Verilog, it
was not chosen for the Digital Basics Courses and that's why
we continue in our course with VHDL, that we consider more
convenient for teaching.<br>
</div>
<div><br>
</div>
Sincerely yours,<br>
<br>
</div>
Pablo Cayuela<br>
<br>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Tue, Feb 16, 2016 at 2:22 PM, Walter
Gallegos <span dir="ltr"><<a moz-do-not-send="true"
href="mailto:walter@waltergallegos.com" target="_blank">walter@waltergallegos.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">I've
waited long time before post this topic because could be
misunderstood, believe me this is a positive post. Try to
address a methodology issue in RISC 5 implementation.<br>
<br>
The gold rule is "FPGA design must be synchronous". Have a
clock do not means synchronous.<br>
<br>
Building the hardware from Verilog description.<br>
<br>
DCM_SP #( .CLK_FEEDBACK("NONE"), .CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(2),<br>
.CLKFX_MULTIPLY(5), .CLKIN_DIVIDE_BY_2("FALSE"),<br>
.CLKIN_PERIOD(16.667), .CLKOUT_PHASE_SHIFT("NONE"),<br>
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),<br>
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),<br>
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE") )<br>
dcm ( .CLKIN(OSCIN), .CLKFX(clkfx), .CLKFB(1'b0),
.RST(1'b0),<br>
.DSSEN(1'b0), .PSCLK(1'b0), .PSEN(1'b0),
.PSINCDEC(1'b0),<br>
.CLKDV(), .CLKFX180(), .CLK0(), .CLK2X(), .CLK2X180(),<br>
.CLK90(), .CLK180(), .CLK270(), .LOCKED(), .PSDONE(),
.STATUS());<br>
<br>
This implement a DCM with OSCIN as input clock to generate
clkfx; for DCMs the XILINX recommend some period in reset
with CLKIN active and stable. Work yes, recommended no. Is
also a good practice rebuild the input clock with the DCM
and not only generate a new one.<br>
<br>
always @(posedge clkfx) begin<br>
clk0 <= ~clk0 & ~clk1; This implement a FF
feeback = not clk0 and not clk1.<br>
clk1 <= clk0; clk1 is also
another FF taking clk0 as data.<br>
pclk <= ~pclk; pclk is a FF
feedback Q in D<br>
end<br>
<br>
Please note, clk0, clk1 and pclk are not aligned, they are
different FF with different placement and routing.<br>
If used as clock, this one of the worst cases, edges are
closed, not the same, routed into uncontrolled skew general
propose routing resources, don't forget of metastability.<br>
<br>
Next,<br>
<br>
always @(posedge clk0) clk <= ~clk;<br>
<br>
"posedge" force the implementation tool to use the clock
edge detection available in each FPGA FF; so, this sentence
force the tool to connect a general purpose interconnection
network as FF output is to the clock distribution tree.<br>
<br>
And again a signal ( not a clock in the FPGA world ) is used
as clock.<br>
<br>
always @(posedge clk)<br>
....<br>
end<br>
<br>
There are also another hidden problem, the RISC clock clk,
that was generated in the logic farm, is not aligned with
clkfx by a variable unknown delay. This delay depend of
several factor as temperature, power supply voltage and
implementation run, that means in two implementation runs of
same code as the tool could select different placement and
routing could result in different delays.<br>
<br>
The correct way to handle clock is with a clock manager; I
strong recommend avoid clock dividers in logic. The
challenge is select a correct oscillator and/or the
appropriate multiply divide parameters.<br>
<br>
And after correct this problems don't forget to modify :<br>
<br>
assign SRwe0 = ~wr | clk, SRwe1 = SRwe0;<br>
<br>
Here clk is used as signal, so if clk is a clock must not be
connected to a LUT input.<br>
<br>
Regards,<span class="HOEnZb"><font color="#888888"><br>
<br>
-- <br>
<br>
Walter Daniel Gallegos<br>
Programmable Logic & Software<br>
Consultoría, Diseño, Entrenamiento.<br>
Montevideo, Uruguay<br>
EMAIL <a moz-do-not-send="true"
href="mailto:walter@waltergallegos.com"
target="_blank">walter@waltergallegos.com</a><br>
Tel +598 26 23 44 60 | Cel +598 99 18 58 88<br>
<br>
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</font></span></blockquote>
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</blockquote>
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<pre class="moz-signature" cols="72">--
Walter Daniel Gallegos
Programmable Logic & Software
Consultoría, Diseño, Entrenamiento.
Montevideo, Uruguay
EMAIL <a class="moz-txt-link-abbreviated" href="mailto:walter@waltergallegos.com">walter@waltergallegos.com</a>
Tel +598 26 23 44 60 | Cel +598 99 18 58 88
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