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John,<br>
Your comment about "what customizations are people considering"
goads me to respond.<br>
<br>
Background: I am currently converting "Deep Learning" to Component
Pascal to understand<br>
what all the excitement is about. <br>
<br>
<a
href="http://www.nature.com/news/google-ai-algorithm-masters-ancient-game-of-go-1.19234">Google
AI algorithm masters ancient game of Go</a><br>
<br>
Also <br>
<br>
<a
href="http://www.wired.com/2016/02/android-inventor-andy-rubin-playground-artificial-intelligence/">Andy
Rubin Unleashed Android on the World. Now Watch Him Do the Same
With AI</a>
<div class="moz-cite-prefix"><br>
Those two stories in the context of Oberon suggests to me that a
world of "minds"<br>
similar to the <a
href="https://en.wikipedia.org/wiki/Internet_of_Things">internet
of things</a> could be implemented on a vast number of devices.<br>
The "collective" would be continually processing and sharing
information; collected<br>
locally and shared globally.<br>
<br>
My background is a mixture of physics and machine learning (speech
recognition) so<br>
my thoughts tend to run in those directions.<br>
<br>
-Doug Danforth<br>
<br>
On 2/15/2016 9:59 PM, <a class="moz-txt-link-abbreviated" href="mailto:jwr@robrts.net">jwr@robrts.net</a> wrote:<br>
</div>
<blockquote
cite="mid:20160215225906.Horde.KJxov_lf2SPm2VYl-adHPj0@kent.machighway.com"
type="cite">What FPGA-related Project Oberon customizations are
people considering or implementing?
<br>
<br>
At <a class="moz-txt-link-freetext" href="http://oberonstation.x10.mx/smf/index.php?topic=26.0">http://oberonstation.x10.mx/smf/index.php?topic=26.0</a> I posted
some questions about how the OberonStation is being used, and what
projects and ideas others are pondering. My questions can easily
be expanded beyond the OberonStation, to any and all of the
Project Oberon 2013 implementations. Within Chris Burrows'
response, he indicated "The opportunities for customising the FPGA
hardware are what excites me about RISC5 Oberon." That is a
particularly interesting observation, and I wonder what types of
customizations others are considering or are already actively
implementing?
<br>
<br>
One possibility includes enhancement of the RISC5 CPU to include
particular special features. [Given that it's supposed to be a
REDUCED I.S.C,, which small enhancements would still be
desirable?] Other possibilities might involve modification of the
display to implement color graphics, or to use some of the I/O
pins to implement a different network communication interface.
I'm interested in parallel programming, so perhaps some kind of
co-processor or multi-core RISC instantiation (perhaps requiring
movement toward AOS/A2 concepts) is of interest.
<br>
<br>
What particular types of "hardware" modification within the FPGA
[i.e. implemented primarily via changes to the Verilog code] do
you think are of interest?
<br>
<br>
-- John Roberts
<br>
<br>
--
<br>
<a class="moz-txt-link-abbreviated" href="mailto:Oberon@lists.inf.ethz.ch">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related
systems
<br>
<a class="moz-txt-link-freetext" href="https://lists.inf.ethz.ch/mailman/listinfo/oberon">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a>
<br>
<br>
</blockquote>
<br>
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