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Magnus<br>
<br>
"This logic signal <i>clk</i> is then connected to a clock buffer
BUFG that will feed one of the global clock nets"<br>
<br>
My apologies, clk routing is : <br>
<br>
The logic clk signal -using general propose routing lines and
connection matrix- is connected to a clock buffer to be able to be
connected to FF edge detectors. This is the only way that the tool
can address the HDL definition.<br>
<br>
So, RISC5 use general propose resources to routing a clock signal. <br>
<br>
Walter.<br>
<br>
<br>
<div class="moz-cite-prefix">El 2016-02-16 a las 16:06, Magnus
Karlsson escribió:<br>
</div>
<blockquote cite="mid:56C37326.8050505@saanlima.com" type="cite">
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<div class="moz-cite-prefix">On 2/16/2016 9:22 AM, Walter Gallegos
wrote:<br>
</div>
<blockquote cite="mid:56C35ABD.6010900@waltergallegos.com"
type="cite"><br>
always @(posedge clk0) clk <= ~clk; <br>
<br>
"posedge" force the implementation tool to use the clock edge
detection available in each FPGA FF; so, this sentence force the
tool to connect a general purpose interconnection network as FF
output is to the clock distribution tree. <br>
<br>
And again a signal ( not a clock in the FPGA world ) is used as
clock. <br>
<br>
always @(posedge clk) <br>
.... <br>
end <br>
<br>
</blockquote>
<br>
No, this is not the way it works. The tool is smart enough to
understand what you really mean and will instantiate the
appropriate modules as needed.<br>
<br>
In the Pepino case, this is how the clock path looks like (as
evident by looking at the fully routed design in Xilinx FPGA
Editor):<br>
The CPU clock signal clk is created by a flip-flop that divides
the input clock CLK50M by 2. This logic signal <i>clk</i> is
then connected to a clock buffer BUFG that will feed one of the
global clock nets. The global clock signal is called <i>clk_BUFG</i>
and is used every where you use it as a clock in the code, as in
the <i>always @(posedge clk)</i> statement.<br>
<br>
<blockquote cite="mid:56C35ABD.6010900@waltergallegos.com"
type="cite">And after correct this problems don't forget to
modify : <br>
<br>
assign SRwe0 = ~wr | clk, SRwe1 = SRwe0; <br>
<br>
Here clk is used as signal, so if clk is a clock must not be
connected to a LUT input. <br>
<br>
</blockquote>
<br>
Again, not a problem. The tool is smart enough to understand that
when you use the signal clk as a logic signal it will use the
non-buffered signal <i>clk</i> and not the buffered signal <i>clk_BUFG</i>.<br>
<br>
Magnus<br>
<br>
<br>
<br>
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<pre class="moz-signature" cols="72">--
Walter Daniel Gallegos
Programmable Logic & Software
Consultoría, Diseño, Entrenamiento.
Montevideo, Uruguay
EMAIL <a class="moz-txt-link-abbreviated" href="mailto:walter@waltergallegos.com">walter@waltergallegos.com</a>
Tel +598 26 23 44 60 | Cel +598 99 18 58 88
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