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<div class="moz-cite-prefix">On 2/16/2016 11:37 AM, Walter Gallegos
wrote:<br>
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<blockquote cite="mid:56C37A96.7010801@waltergallegos.com"
type="cite">
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Magnus<br>
<br>
"This logic signal <i>clk</i> is then connected to a clock buffer
BUFG that will feed one of the global clock nets"<br>
<br>
My apologies, clk routing is : <br>
<br>
The logic clk signal -using general propose routing lines and
connection matrix- is connected to a clock buffer to be able to be
connected to FF edge detectors. This is the only way that the tool
can address the HDL definition.<br>
<br>
So, RISC5 use general propose resources to routing a clock signal.
<br>
<br>
Walter.<br>
<br>
</blockquote>
<br>
There is absolutely nothing wrong with generating a clock signal
like this. <br>
Yes, the output from the flip-flop is routed using general routing
resources, there is no other option. But after it's sent through
the BUFG it's a perfectly legit clock signal.<br>
<br>
I have created a small project to demonstrate this, it's available
on GitHub and it will only take ISE a few seconds to generated a bit
file. <br>
<b>ISE will go through this project without a single warning being
generated.</b> Anyone with ISE experience will tell you that it
will generate warning for every little detail it will find
questionable.<br>
<br>
The project is available here:
<a class="moz-txt-link-freetext" href="https://github.com/Saanlima/Pepino/tree/master/Projects/Pepino_clktest">https://github.com/Saanlima/Pepino/tree/master/Projects/Pepino_clktest</a><br>
<br>
Magnus<br>
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