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<div class="moz-cite-prefix">On 2/16/2016 11:52 AM, Walter Gallegos
wrote:<br>
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<blockquote cite="mid:56C37DED.50900@waltergallegos.com" type="cite">
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Magnus,<br>
<br>
<i>always @ (posedge CLK50M) clk <= ~clk;<br>
<br>
</i>This is also a bad practice. clk edge are not aligned with
CLK50M in a uncontrolled fashion. So, this is a kind of
asynchronism for the rest of FPGA.<br>
<br>
Walter<br>
<br>
</blockquote>
No, not bad practice at all!<br>
<br>
The input signal CLK50M is only used in one place and that is to
create the signal clk. The signal clk does not need to be aligned
with CLK50M in any fashion since it's never used by any logic
clocked by CLK50M.<br>
If you believe there is a problem here then point us to the line in
the code where this problem exist.<br>
<br>
Magnus<br>
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