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<div class="moz-cite-prefix">>> With this DCM configuration :
clk = CLK0 = CLKIN = 50 MHZ<br>
No, I don't think so. I set CLKIN_DIVIDE_BY_2 to TRUE which will
divide the input clock by 2 before it enters the DCM, and the
monitor is syncing at 1024x768@70 Hz so pclk is definitely not 150
MHz.<br>
<br>
I fund the real problem though: what you call CLK25F90 is really
clk shifted by 270 deg, not 90 deg!<br>
<br>
I changed the DCM code to reflect this:<br>
<br>
<font face="Courier New, Courier, monospace">DCM
#(.CLKFX_MULTIPLY(3), .CLKIN_DIVIDE_BY_2("TRUE"),
.CLKIN_PERIOD(20.000))<br>
dcm(.CLKIN(CLK50M), .CLKFB(clk), .RST(1'b0), .PSEN(1'b0),<br>
.PSINCDEC(1'b0), .PSCLK(1'b0), .DSSEN(1'b0), .CLKFX(pclk),
.CLK0(clk),<br>
.CLK270(clk270));<br>
<br>
ODDR2 #(.INIT(1'b1))<br>
oddr2(.Q(wr_enable), .C0(clk270), .C1(~clk270), .CE(1'b1),
.D0(1'b1),<br>
.D1(~wr), .R(1'b0), .S(1'b0));</font><br>
<br>
<font face="Courier New, Courier, monospace">assign SRwe =
wr_enable;</font><br>
<br>
And with that code change it now runs fine on the Pepino board.<br>
<br>
So I guess we have four alternatives that seems to run fine:<br>
* The original code where clk is generated by a flip-flop<br>
* The fully-synchronous version where everything is clocked by a
75 MHz clock generated by DCM<br>
* The version using DCM where the write-enable signal is generated
by a 50 MHz clock<br>
* The version using DCM where the write-enable signal is generated
using a DDR output buffer<br>
<br>
Just pick and choose ;)<br>
<br>
Cheers,<br>
Magnus<br>
<br>
On 2/24/2016 5:37 AM, Walter Gallegos wrote:<br>
</div>
<blockquote cite="mid:56CDB22C.3050908@waltergallegos.com"
type="cite">
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You are welcome !<br>
<br>
With this DCM configuration : clk = CLK0 = CLKIN = 50 MHZ<br>
<br>
Here my simulation using Cypress SRAM VHDL simulation model with
ALDEC simulator.<br>
<br>
Label : "Potential Issue", If you read the SRAM and - in the next
clk cycle - try to write the same SRAM data bus we could wait some
ns of bus contention near this point.<br>
If RISC5 can read then write in consecutive clk cycles the issue
is easy worked capturing de SRAM data with 90° clock and releasing
oen soon.<br>
<br>
<img src="cid:part1.06010701.02020407@saanlima.com" alt=""><br>
<br>
<br>
About your solution is fully synchronous it's ok considering that
both clocks come from same DCM.<br>
<br>
Best regards,<br>
Walter<br>
<br>
<div class="moz-cite-prefix">El 2016-02-23 a las 14:28, Magnus
Karlsson escribió:<br>
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Since the ETH Oberon mailing list seems to delay our posts by a
few days I decided to send it directly to you as well.<br>
<br>
Magnus<br>
<div class="moz-forward-container"><br>
<br>
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<th align="RIGHT" nowrap="nowrap" valign="BASELINE">Subject:
</th>
<td>Re: [Oberon] RISC5 implementation issues.</td>
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<th align="RIGHT" nowrap="nowrap" valign="BASELINE">Date:
</th>
<td>Tue, 23 Feb 2016 08:49:05 -0800</td>
</tr>
<tr>
<th align="RIGHT" nowrap="nowrap" valign="BASELINE">From:
</th>
<td>Magnus Karlsson <a moz-do-not-send="true"
class="moz-txt-link-rfc2396E"
href="mailto:magnus@saanlima.com"><magnus@saanlima.com></a></td>
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<th align="RIGHT" nowrap="nowrap" valign="BASELINE">To:
</th>
<td>ETH Oberon and related systems <a
moz-do-not-send="true" class="moz-txt-link-rfc2396E"
href="mailto:oberon@lists.inf.ethz.ch"><a class="moz-txt-link-rfc2396E" href="mailto:oberon@lists.inf.ethz.ch"><oberon@lists.inf.ethz.ch></a></a></td>
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<div class="moz-cite-prefix">Walter,<br>
<br>
I tried your proposed solution and couldn't make it work.
It "almost" works in that it starts the boot process and
reads from the SD-card, but then hangs with the LEDs showing
0x84.<br>
Maybe I didn't do it correct, I instantiated the ODDR2
buffer directly at the top module and modified the DCM
instantiation to create the clk90 clock.<br>
<br>
Here is the code, can you look it over and see if this is
what you had in mind or if something is wrong:<br>
<br>
<font face="Courier New, Courier, monospace">DCM
#(.CLKFX_MULTIPLY(3), .CLKIN_DIVIDE_BY_2("TRUE"),
.CLKIN_PERIOD(20.000))<br>
dcm(.CLKIN(CLK50M), .CLKFB(clk), .RST(1'b0),
.PSEN(1'b0),<br>
.PSINCDEC(1'b0), .PSCLK(1'b0), .DSSEN(1'b0),
.CLKFX(pclk), .CLK0(clk),<br>
.CLK90(clk90));<br>
<br>
ODDR2 #(.INIT(1'b1))<br>
oddr2(.Q(wr_enable), .C0(clk90), .C1(~clk90), .CE(1'b1),
.D0(1'b1),<br>
.D1(~wr), .R(1'b0), .S(1'b0));</font><br>
<br>
<font face="Courier New, Courier, monospace">assign SRwe =
wr_enable;<br>
<br>
</font><br>
wr is the active-high write signal from the RISC5 CPU, and
SRwe is the short active-low write-enable signal to the
SRAM.<br>
<br>
Just to recap, this is the code I used to generate the short
write pulse, using a 2x clk instead. This version seems to
run fine:<br>
<br>
<font face="Courier New, Courier, monospace">reg wr_enable;</font><br>
<br>
<font face="Courier New, Courier, monospace">DCM
#(.CLKFX_MULTIPLY(3), .CLKFX_DIVIDE(2), .CLKDV_DIVIDE(2),
.CLKIN_PERIOD(20.000))<br>
dcm(.CLKIN(CLK50M), .CLKFB(clk2x), .RST(1'b0),
.PSEN(1'b0),<br>
.PSINCDEC(1'b0), .PSCLK(1'b0), .DSSEN(1'b0),
.CLKFX(pclk), .CLKDV(clk), .CLK0(clk2x));<br>
<br>
always @(negedge clk2x)<br>
wr_enable <= wr & ~wr_enable;<br>
<br>
assign SRwe = ~wr_enable;<br>
<br>
</font><br>
Any idea what's wrong?<br>
Magnus<br>
<br>
<br>
On 2/19/2016 9:58 AM, Walter Gallegos wrote:<br>
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<blockquote cite="mid:56C757AE.5070807@waltergallegos.com"
type="cite">
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Let us concentrate in the problem...<br>
<br>
How to generate an output pulse shorter than clock period?<br>
<br>
You can make a pulse shorter with help of DCM and DDR ( dual
data rate output registers ) see the simulation capture <br>
<br>
<img src="cid:part4.01070706.07060406@saanlima.com" alt=""><br>
<br>
clk25f90 is the DCM clock output with 90° phase shift.<br>
<br>
The VHDL code is : ( without DCM instantiation )<br>
<br>
ENTITY PulseShaper IS<br>
PORT (CLK25F90 : IN STD_LOGIC;<br>
RESET : IN STD_LOGIC;<br>
WE : IN STD_LOGIC;<br>
WESRAM : OUT STD_LOGIC<br>
);<br>
END PulseShaper;<br>
<br>
ARCHITECTURE RTL OF PulseShaper IS<br>
<br>
CONSTANT zero : STD_LOGIC := '0';<br>
CONSTANT one : STD_LOGIC := '1';<br>
<br>
SIGNAL clk90n: STD_LOGIC;<br>
<br>
BEGIN<br>
<br>
clk90n <= NOT(CLK25F90); -- This is valid because the
tool use the clock inverter available in IOB<br>
<br>
Dly : ODDR2<br>
PORT MAP (<br>
Q => WESRAM, <br>
C0 => CLK25F90, <br>
C1 => clk90n, <br>
CE => one, <br>
D0 => one, <br>
D1 => WE, <br>
R => zero, <br>
S => zero <br>
);<br>
<br>
END RTL;<br>
<br>
Someone know if exist a FPGA testbench for RISC5 ?<br>
<br>
Regards,<br>
Walter
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