<html><body>Hi Paul,<div><br></div><div>Thank you, now I can see btn `sticking out' in the code.</div><div><br></div><div>Given the information here, I have had a second thought about the reset, perhaps command abort is more useful after all, the means to step out from an endless loop. (I remember from a distant past, Macintosh had Apple+.(dot) key abort sequence)</div><div><br></div><div>Reset can always be triggered by cycling the power over USB connector.</div><div><br></div><div>I may try to install a microswitch over pin header btn3 and 3.3V, for a start.</div><div><br></div><div>My next exercise then might be to modify verilog source to tie btn3 to the onboard push button, I am examining Icarus capabilities at the moment. To understand verilog will be a long process, I can see.</div><div><br></div><div>Paul, my another challenge is to implement your network time client, I have read your papers you lectured at ETH. But seems too shorthand for me at the moment, to understand fully.</div><div><br></div><div>I may be also getting nordic module, that is required I believe for this. It would be nice to have ticking clock, and see real time stamps on files :-) </div><div><br></div><div>Many thanks so far.</div><div>Tomas</div><div><br></div><div><br><p>---------- Původní zpráva ----------<br>Od: Paul Reed <email@example.com><br>Komu: ETH Oberon and related systems <firstname.lastname@example.org><br>Datum: 22. 3. 2017 20:43:42<br>Předmět: Re: [Oberon] FPGA Oberon - Reset Button</p><br><blockquote>Hi Tomas,
<br>> I wish to install reset switch, which pin header / button is the reset?
<br>> Connector J8
<br>> 5V GND GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7
<br>> 3.3V GND BTN0 BTN1 BTN2 BTN3 N/C N/C N/C N/C
<br>On the Spartan 3 board btn3 is marked "User Reset" but since you have (I
<br>believe) a Pepino you wouldn't necessarily know that. :)
<br>The relevant line in Prof. Wirth's Verilog is in RISC5Top.v, near the bottom:
<br>always @(posedge clk)
<br> rst <= ((cnt1[4:0] == 0) & limit) ? ~btn : rst;
<br>Note that this reset merely aborts the current Oberon command and returns
<br>to the main loop, like the Interrupt key on the Ceres.
<br>There isn't an I/O signal which does a cold reset of the Oberon system in
<br>the way a PC reset button works, since the Spartan 3 board has a
<br>pushbutton called "Prog" which reloads the FPGA configuration (forcing a
<br>complete cold start of the hardware).
<br>From the Pepino schematic it looks like Magnus has the Spartan 6 FPGA PROG
<br>pin just pulled high (signal PROGRAM_B) by resistor R32. You could try
<br>grounding the other side of the resistor to get the same effect as the
<br>PROG button - but take care not to destroy your board obviously!
<br>There is a pushbutton on the Pepino, marked "BUTTON" on the schematic, but
<br>you'd have to change the Verilog and reprogram the board if you wanted to
<br>use that as btn3.
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