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--></style></head><body bgcolor=white lang=DE link="#0563C1" vlink="#954F72"><div class=WordSection1><p class=MsoPlainText><span lang=EN-US>Hi Wojtek<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>Are you saying FPGA can not implement this:?<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span style='mso-fareast-language:DE'><img width=522 height=266 id="Bild_x0020_1" src="cid:image001.png@01D33FB0.F72AFD20"></span><span lang=EN-US><o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText>Am 07.10.17, 20:26 schrieb "Oberon im Auftrag von Skulski, Wojciech" <oberon-bounces@lists.inf.ethz.ch im Auftrag von skulski@pas.rochester.edu>:<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText> Joerg:<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> These clock manipulations look interesting. I wonder how ISE or Vivado translate these into logic. Combinatorial clocks cannot be used in FPGA designs. Combinatorial means "derived from logic equations" like the ones we see below. The reason is that the clocking inputs to flip flops are seldom (if ever) directly connected to the fabric, where such equations are implemented in hardware. And even if such connections exist (I doubt they do), using them is strongly discouraged by the FPGA manufacturers. Maybe ISE tools are smart enough to somehow pack these equations into the Digital Clock Manager (DCM)? <o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> So it is an interesting piece of HDL which is calling either for a rework or for examination of the translation report to find out, how it is implemented by the tools. If you want to divide the clock by five, then I am pretty sure the DCM will need to be used.<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> Concerning the SPI, it can run at a wide range of frequencies. Perhaps some part has some special requirements, which then need to be dealt with locally in the respective HDL module. <o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> W.<o:p></o:p></p><p class=MsoPlainText> ________________________________________<o:p></o:p></p><p class=MsoPlainText> For the OberonStation, RISC5Top.v looks like this:<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> always @(posedge clk0) clk <= ~clk;<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> always @(posedge clkfx) begin<o:p></o:p></p><p class=MsoPlainText> clk0 <= ~clk0 & ~clk1; clk1 <= clk0;<o:p></o:p></p><p class=MsoPlainText> pclk <= ~pclk;<o:p></o:p></p><p class=MsoPlainText> end<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> clkfx runs at 150 MHz<o:p></o:p></p><p class=MsoPlainText> pcclk runs at 75 MHz (VGA timing)<o:p></o:p></p><p class=MsoPlainText> clk0 runs at 50 MHz<o:p></o:p></p><p class=MsoPlainText> clk runs at 25 MHz<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> So, instead of dividing by 3 and then by 2 to get to clk, we would need to divide clkfx by 5.<o:p></o:p></p><p class=MsoPlainText> Of course the SPI divider „tick“ needs to adopted from 63 to 75 and so on. (400 kHz = 25MHz / 63 = 30 MHz / 75)<o:p></o:p></p><p class=MsoPlainText> Sorry, I forgot to mention these details.<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p><p class=MsoPlainText> --<o:p></o:p></p><p class=MsoPlainText> Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems<o:p></o:p></p><p class=MsoPlainText> https://lists.inf.ethz.ch/mailman/listinfo/oberon<o:p></o:p></p><p class=MsoPlainText> <o:p></o:p></p></div></body></html>