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--></style></head><body lang=DE-CH link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>The board has two entities you might use to run AOS<o:p></o:p></span></p><ul style='margin-top:0cm' type=disc><li class=MsoListParagraph style='margin-left:0cm;mso-list:l0 level1 lfo1'><span lang=EN-US style='mso-fareast-language:EN-US'>the ARM processor (Cortex M0+)<o:p></o:p></span></li><li class=MsoListParagraph style='margin-left:0cm;mso-list:l0 level1 lfo1'><span lang=EN-US style='mso-fareast-language:EN-US'>the Cyclone FPGA could be programmed to be a Cortex M1 or RISC-5 processor.<o:p></o:p></span></li></ul><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>Run AOS on ARM or port AOS to RISC-5<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>br<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>Jörg<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span style='font-size:12.0pt;color:black'>Von: </span></b><span style='font-size:12.0pt;color:black'>Oberon <oberon-bounces@lists.inf.ethz.ch> im Auftrag von Søren Renner <soren.renner@gmail.com><br><b>Antworten an: </b>ETH Oberon and related systems <oberon@lists.inf.ethz.ch><br><b>Datum: </b>Mittwoch, 25. Juli 2018 um 13:51<br><b>An: </b><oberon@lists.inf.ethz.ch><br><b>Betreff: </b>Re: [Oberon] Oberon Digest, Vol 170, Issue 3<o:p></o:p></span></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Is this board going to run Active Oberon (A2 OS)? <o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Wed, Jul 25, 2018 at 6:00 AM, <<a href="mailto:oberon-request@lists.inf.ethz.ch" target="_blank">oberon-request@lists.inf.ethz.ch</a>> wrote:<o:p></o:p></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm'><p class=MsoNormal>Send Oberon mailing list submissions to<br> <a href="mailto:oberon@lists.inf.ethz.ch">oberon@lists.inf.ethz.ch</a><br><br>To subscribe or unsubscribe via the World Wide Web, visit<br> <a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a><br>or, via email, send a message with subject or body 'help' to<br> <a href="mailto:oberon-request@lists.inf.ethz.ch">oberon-request@lists.inf.ethz.ch</a><br><br>You can reach the person managing the list at<br> <a href="mailto:oberon-owner@lists.inf.ethz.ch">oberon-owner@lists.inf.ethz.ch</a><br><br>When replying, please edit your Subject line so it is more specific<br>than "Re: Contents of Oberon digest..."<br><br><br>Today's Topics:<br><br> 1. New Hardware for Oberon / Risc-5 ? (greim)<br> 2. Re: New Hardware for Oberon / Risc-5 ? (J?rg)<br> 3. RiskFive: New Hardware for Oberon / RISC5 ? (Skulski, Wojciech)<br> 4. Wanted: Oberon Syntax in TextMate, Sublime Text or Atom<br> Grammar (Treutwein Bernhard)<br><br><br>----------------------------------------------------------------------<br><br>Message: 1<br>Date: Tue, 24 Jul 2018 12:10:45 +0200<br>From: greim <<a href="mailto:greim@schleibinger.com">greim@schleibinger.com</a>><br>To: <a href="mailto:oberon@lists.inf.ethz.ch">oberon@lists.inf.ethz.ch</a><br>Subject: [Oberon] New Hardware for Oberon / Risc-5 ?<br>Message-ID: <<a href="mailto:153b9dd9-b20e-b51e-96d9-798a30bf1d2e@schleibinger.com">153b9dd9-b20e-b51e-96d9-798a30bf1d2e@schleibinger.com</a>><br>Content-Type: text/plain; charset=utf-8; format=flowed<br><br>Hello,<br><br>Arduinio brought a brand new FPGA board to the market!<br>Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM<br><br><a href="https://store.arduino.cc/arduino-vidor-4000" target="_blank">https://store.arduino.cc/arduino-vidor-4000</a><br><br>Not much info yet.<br>Seems they will build the future software on System Verilog.<br>And maybe they create also a Verilog dev. platform on the web.<br>Could imagine that Intel will support it. Their standing in the embedded <br>world is friendly spoken quite weak up to now.<br><br>But Arduinio was a success story up to now, so I am optimistic that they<br>will bring FPGA programming to the people, as they did with <br>microcontroller programming.<br><br>Could any body say if the Cyclone 10CL016 is powerful enough to handle <br>the Oberon system?<br><br>Bringing Oberon and Arduinio together would be a big step ahead for <br>Oberon / Risc-5, I think.<br><br>Markus<br><br><br><br>------------------------------<br><br>Message: 2<br>Date: Tue, 24 Jul 2018 13:27:45 +0200<br>From: J?rg <<a href="mailto:joerg.straube@iaeth.ch">joerg.straube@iaeth.ch</a>><br>To: <<a href="mailto:greim@schleibinger.com">greim@schleibinger.com</a>><br>Cc: ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch">oberon@lists.inf.ethz.ch</a>><br>Subject: Re: [Oberon] New Hardware for Oberon / Risc-5 ?<br>Message-ID: <<a href="mailto:03084B12-A275-4EC3-8812-02BC57554A96@iaeth.ch">03084B12-A275-4EC3-8812-02BC57554A96@iaeth.ch</a>><br>Content-Type: text/plain; charset="UTF-8"<br><br>Markus<br><br><br><br>Comparing FPGAs 1:1 is difficult. The RISC-5 CPU fits in a LX9.<br><br>- LX9 has 9K logic cells, 576 kbits memory, 200 IO<br><br>- CL016 has 16k logic cells, 504 kbits memory, 340 IO<br><br><br><br>>From the order of magnitude Oberon should fit<br><br><br><br>J?rg<br><br><br><br>?Am 24.07.18, 12:12 schrieb "Oberon im Auftrag von greim" <<a href="mailto:oberon-bounces@lists.inf.ethz.ch">oberon-bounces@lists.inf.ethz.ch</a> im Auftrag von <a href="mailto:greim@schleibinger.com">greim@schleibinger.com</a>>:<br><br><br><br> Hello,<br><br><br><br> Arduinio brought a brand new FPGA board to the market!<br><br> Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM<br><br><br><br> <a href="https://store.arduino.cc/arduino-vidor-4000" target="_blank">https://store.arduino.cc/arduino-vidor-4000</a><br><br><br><br> Not much info yet.<br><br> Seems they will build the future software on System Verilog.<br><br> And maybe they create also a Verilog dev. platform on the web.<br><br> Could imagine that Intel will support it. Their standing in the embedded <br><br> world is friendly spoken quite weak up to now.<br><br><br><br> But Arduinio was a success story up to now, so I am optimistic that they<br><br> will bring FPGA programming to the people, as they did with <br><br> microcontroller programming.<br><br><br><br> Could any body say if the Cyclone 10CL016 is powerful enough to handle <br><br> the Oberon system?<br><br><br><br> Bringing Oberon and Arduinio together would be a big step ahead for <br><br> Oberon / Risc-5, I think.<br><br><br><br> Markus<br><br><br><br> --<br><br> <a href="mailto:Oberon@lists.inf.ethz.ch">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related systems<br><br> <a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a><br><br><br><br><br><br><br><br>------------------------------<br><br>Message: 3<br>Date: Tue, 24 Jul 2018 12:54:13 +0000<br>From: "Skulski, Wojciech" <<a href="mailto:skulski@pas.rochester.edu">skulski@pas.rochester.edu</a>><br>To: ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch">oberon@lists.inf.ethz.ch</a>>,<br> "<a href="mailto:greim@schleibinger.com">greim@schleibinger.com</a>" <<a href="mailto:greim@schleibinger.com">greim@schleibinger.com</a>><br>Subject: [Oberon] RiskFive: New Hardware for Oberon / RISC5 ?<br>Message-ID:<br> <<a href="mailto:CY1PR07MB26343995145E1B18C465FE42FF550@CY1PR07MB2634.namprd07.prod.outlook.com">CY1PR07MB26343995145E1B18C465FE42FF550@CY1PR07MB2634.namprd07.prod.outlook.com</a>><br><br>Content-Type: text/plain; charset="us-ascii"<br><br>All:<br><br>Concerning the new hardware, I reworked RiskFive after realizing that the DDR3 memory is bringing significant problems to the system design, such as latencies and caching. So I decided to develop a new version of that board with ZBT RAM. I released the information two days ago on the website RiskFive.com. Today I received the quote for building the "bone" board. This night I finished the motherboard files to be sent for the quote. We will build these boards.<br><br>Mind it, RiskFive will be an expensive board. It is meant to be a development platform from which a future board/boards will emerge. For example, there are two 100M Ethernet channels on the motherboard. Obviously, for a practical application you need only one. I am providing two Ethernet chips for the development of two application tiers. Then there is the USB-3 channel for something really fast like data streaming. An interesting spin is that you can map the entire board memory on the USB-3 interface and dump it to the PC. <br><br>A significant goal is the 24 bit color. I provided a professional video DAC rather trying to simulate it with a bunch of el cheapo resistors. The ZBT architecture will allow to develop a very efficient and very simple video channel with 8-bit pixel mapped to 24-bit color via a lookup table (a "palette").<br><br>Concerning System Verilog, professor Pong Chu just published his Verilog version of his SOC design book. I received the copy three days ago. It looks magnificent. Highly recommended! Professor Chu is using Artix-7, the exact same chip which I am using on RiskFive. The entire firmware framework is now available from Professor Pong website, both in VHDL and in System Verilog. We do not need to scrounge around for firmware bits and pieces, because a high quality FPro framework is now available. <br><br>My intent is open hardware. The motherboard design files will be released as soon as I actually order this board. The FOM design files will be available in PDF to everyone, and in full source on request. <br><br>Thank you,<br>Wojtek<br><br>------------------------------<br><br>Message: 4<br>Date: Tue, 24 Jul 2018 13:50:05 +0000<br>From: Treutwein Bernhard<br> <<a href="mailto:Bernhard.Treutwein@Verwaltung.Uni-Muenchen.DE">Bernhard.Treutwein@Verwaltung.Uni-Muenchen.DE</a>><br>To: "'<a href="mailto:oberon@lists.inf.ethz.ch">oberon@lists.inf.ethz.ch</a>'" <<a href="mailto:oberon@lists.inf.ethz.ch">oberon@lists.inf.ethz.ch</a>><br>Subject: [Oberon] Wanted: Oberon Syntax in TextMate, Sublime Text or<br> Atom Grammar<br>Message-ID:<br> <<a href="mailto:78A8BD6765DCF048A628A51C3FBD1D7659B44E66@MXS2.zuv.uni-muenchen.de">78A8BD6765DCF048A628A51C3FBD1D7659B44E66@MXS2.zuv.uni-muenchen.de</a>><br>Content-Type: text/plain; charset="iso-8859-1"<br><br>Does somebody have grammars for <br> Oberon / Oberon-2 / Component Pascal / Active Oberon<br>as grammar for<br> TextMate / Sublime Text / Atom <br><br><br>Background: Github wrongly classifies Oberon / Oberon-2 / Component Pascal / Active Oberon<br>as Modula-2. I opened quite some tiome ago an issue in the github/linguist project<br>(<a href="https://github.com/github/linguist/issues/3888" target="_blank">https://github.com/github/linguist/issues/3888</a>) and they don't accept EBNF grammars.<br><br>--<br>? Bernhard Treutwein<br><br><br>------------------------------<br><br>Subject: Digest Footer<br><br>--<br><a href="mailto:Oberon@lists.inf.ethz.ch">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related systems<br><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a><br><br><br>------------------------------<br><br>End of Oberon Digest, Vol 170, Issue 3<br>**************************************<o:p></o:p></p></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>-- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon <o:p></o:p></p></div></body></html>