<html><head></head><body><div style="font-family:Helvetica Neue, Helvetica, Arial, sans-serif;font-size:13px;"><div><span><div> > I realize [Moving oberon to RISC[-]V] is a lot of work,</div><div> > but there's quite a bit of momentum for it.</div><div> > What would need to be done to port Oberon?</div><div><br></div><div><span><div>In essence, you would need to do two things:</div><div><br></div><div>1. Find a suitable hardware board that supports the</div><div> RISC-V instruction set architecture (http://riscv.org)</div><div> or use an emulator with RISC-V support</div><div> such as QEMU (http://github.com/riscv/riscv-qemu)</div><div><br></div><div>2. Change the code generator of the Oberon compiler</div><div> to generate instructions for the RISC-V CPU (see also</div><div> http://oberon.wikidot.com/oberon-linux-revival-olr)</div><div><br></div><div>If you want to port the entire Oberon system, you may</div><div>also need to adapt some inner and outer core modules</div><div>(e.g., Kernel, Display), depending on the HW you use.</div><div><br></div><div>It would set you back 1-3 months, assuming familiarity</div><div>with both the RISC-V processor architecture and the</div><div>Oberon compiler, in particular its code generator.</div><div><br></div><div>-ap</div><div><br></div><div><br></div></span></div></span></div><br></div></body></html>