<html><body><html><head><meta name="viewport" content="width=device-width" /><meta http-equiv="Content-Type" content="text/vnd.ui.insecure+html;charset=utf-8" /></head><body style="overflow-wrap:break-word; word-break: break-word;"><div class="mail_android_message" style="line-height: 1; padding: 0.5em">CPU-cache can be independent from the instruction set. I think Risc-V/Arduino groups should be asked if there will be a RISC-V port. If yes, RISC5 port should also be possible or RISC-V can be used directly (or the ARM part of the board).<br>
<br>
Peter<br>
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sent mobile by neffos </div><div class="mail_android_quote" style="line-height: 1; padding: 0.3em">Am 27.07.18, 11:21, "Jörg" <joerg.straube@iaeth.ch> schrieb:<blockquote class="gmail_quote" style="margin: 0.8ex 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
Simple porting of the RISC-5 willl be difficult to that board as this CPU does not support a cache. First as Wojtek correctly pointed out, it‘s SDRAM, but secondly the AS4C4M16SA-7BCN is organized as 16x 4Mb.<br />
Good, let’s assume the RISC-5 would evolve to RISC-6 adding an instruction and a data cache to overcome the longer SDRAM start time until full transfer speed is reached, this cache has to be used as well to make it look like a 32 bit architecture.<br />
<br />
Jörg<br />
<br />
> Am 27.07.2018 um 03:43 schrieb Skulski, Wojciech <skulski@pas.rochester.edu>:<br />
> <br />
> Markus wrote:<br />
> <br />
>> Arduinio brought a brand new FPGA board to the market!<br />
>> Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM<br />
> <br />
> The website says "onboard 8 Mbyte SDRAM". SDRAM is not SRAM. It is hard to say for sure what they installed because neither the schematic nor the BOM are prominently displayed on that website. Maybe they are there somewhere. But I assume they know what they are saying.<br />
> <br />
> I cancelled my previous Oberon board project after realizing the intricacies of caching. I do not want to say that SDRAM is bad. But I decided to shy away from it. Another concern is indeterministic software execution time, depending on the cache status and thus on execution history. This would be bad for my field of study.<br />
> <br />
> <a href="http://www.arduino.cc/en/Guide/MKRVidor4000">www.arduino.cc/en/Guide/MKRVidor4000</a> <br />
> <br />
> Wojtek<br />
> <br />
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