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--></style></head><body lang=DE-CH link=blue vlink="#954F72"><div class=WordSection1><p class=MsoNormal>Andreas</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The RISC5 processor has an addressbus of 24 bits («adr» in RISC5.v = 16 MB possible).</p><p class=MsoNormal>As the PC and branch displacements are on word boundary, they have 22 bits («disp» in RISC5.v)</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>So, basically, C24 is wrong in the first place, as displacements can not be larger than 22 bits (0..21).</p><p class=MsoNormal>Effectively only +/- 21 bits, as the MSB (bit 21) signals negative branches.</p><p class=MsoNormal>But C24 does not harm as it correctly handles the negative values.</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This explains how ORG.fix() could have been implemented.</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Now, ORG.FixLink and ORG.FixLinkWith handle chains of jump addresses to be fixed. The values in the chain are only positive and they are smaller than ORG.maxCode.</p><p class=MsoNormal>Principally, «MOD maxCode» would be enough. For efficiency, any power of 2 bigger then ORG.maxCode would do, so MOD 40000H does not harm.</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>In short, I would have coded the procedures as follows:</p><p class=MsoNormal><o:p> </o:p></p><div><pre> PROCEDURE FixLink*(L: LONGINT);</pre><pre> VAR L1: LONGINT;</pre><pre> BEGIN</pre><pre> WHILE L # 0 DO L1 := code[L] MOD 2000H; FixOne(L); L := L1 END</pre><pre> END FixLink;</pre></div><p class=MsoNormal><o:p> </o:p></p><div><pre> PROCEDURE FixLinkWith(L0, dst: LONGINT); (* used for «UNTIL» *)</pre><pre> VAR L1: LONGINT;</pre><pre> BEGIN</pre><pre> WHILE L0 # 0 DO</pre><pre> L1 := code[L0] MOD 2000H; fix(L0, dst - L0 - 1); L0 := L1</pre><pre> END</pre><pre> END FixLinkWith;</pre></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>br</p><p class=MsoNormal>Jörg</p><p class=MsoNormal><o:p> </o:p></p><div style='mso-element:para-border-div;border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal style='border:none;padding:0cm'><b>Von: </b><a href="mailto:andreas_pirklbauer@yahoo.com">Andreas Pirklbauer</a><br><b>Gesendet: </b>Sonntag, 23. September 2018 12:26<br><b>An: </b><a href="mailto:oberon@lists.inf.ethz.ch">ETH Oberon and related systems</a><br><b>Betreff: </b>[Oberon] FJump and FixLink</p></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal> > Thanks Jorg. Good pointers.</p><p class=MsoNormal> ></p><p class=MsoNormal> > > - are branch offsets in words or bytes?</p><p class=MsoNormal> ></p><p class=MsoNormal> > In words.</p><p class=MsoNormal> ></p><p class=MsoNormal> >> - how much RAM does the board have?</p><p class=MsoNormal> ></p><p class=MsoNormal> > 1MB SRAM.</p><p class=MsoNormal> ></p><p class=MsoNormal> > Now I see.</p><p class=MsoNormal> > To address 1MB we need = 20 bits If we present offset in words, we need = 20 - 2 = 18 bit. :-) </p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Just to add another remark on this topic. The official Oberon-07 compiler is in fact inconsistent:</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>- in ORG.FixLink: L1 := code[L] MOD 40000H; (*18 bits*)</p><p class=MsoNormal>- in ORG.FixLinkWidth: L1 := code[L0] MOD C24; (*24 bits*)</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Does anyone know why?</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>PS: I would prefer to use C24 throughout. That way the compiler also automatically </p><p class=MsoNormal>works ob boards with larger memories.</p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>--</p><p class=MsoNormal>Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems</p><p class=MsoNormal>https://lists.inf.ethz.ch/mailman/listinfo/oberon</p><p class=MsoNormal><o:p> </o:p></p></div></body></html>