<div dir="ltr">Thanks Jörg,<div><br></div><div>I have made some edits to the technote based on your comments. I hope I have done them justice. </div><div><br></div><div>As far as real hardware goes, I look forward to seeing what the community can do with the new FPGA platforms that are coming available. Before too long I will want to move beyond an emulated system, and I will want a big screen and lots of colors!</div><div><br></div><div>br,</div><div>Chuck</div></div><br><div class="gmail_quote"><div dir="ltr">On Sat, Jan 12, 2019 at 12:05 AM JR <<a href="mailto:joerg.straube@iaeth.ch">joerg.straube@iaeth.ch</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div style="word-wrap:break-word">Chuck<div><br></div><div>Thx for the technote.</div><div><br></div><div>Four remarks:</div><div>- Currently, the display memory is mapped into physical RAM. Hence dynamic changing of display geometries directly influences the amount of RAM available for the heap. You can only do that, if you a) reduce the display geometries or b) when you increase the geometries you have to make sure there are no heap objects allocated in the memory the extended new frame buffer will occupy. You might follow this calculation:</div><div> (physMem = 100000H (* 1MB *); base := physMem - 256 - LINELEN * screenH; MemLim := base - 16).</div><div><br></div><div>- If we want to enlarge the RAM in the future, another way of memory mapping could be envisioned. As display memory is very time critical we could allocate it in SRAM as today, and could use DRAM only for the physical RAM. As RISC-5 is a 32 bit machine, the max address range is 4 GB. So, we could define all addresses <2G can be used for physical RAM, all addresses >2G are used for display, IO addresses and ROM. Then the base address of the display is always the same (=80000000H). The only limiting factor is the size of the SRAM the display address range is mapped into.</div><div><br></div><div>- As the boot loader is written in Oberon, instead of „patching“ you could change the constants stackOrg and MemLim in BootLoad.Mod, recompile it and extract the code.</div><div><br></div><div>- If you want to change the stack size (what I did when implementing the color display on a 1MB machine), you have to take this into account: Unfortunately, the stackSize is defined in Kernel.Mod and a second time in Modules.Mod. Either you change the stackSize consistently at both locations or you import Kernel.stackSize in Modules.</div><div><br></div><div>br</div><div>Jörg</div><div><div><br><blockquote type="cite"><div>Am 11.01.2019 um 20:07 schrieb Charles Perkins <<a href="mailto:chuck@kuracali.com" target="_blank">chuck@kuracali.com</a>>:</div><br class="gmail-m_-4773376675527274754Apple-interchange-newline"><div><div dir="ltr"><div dir="ltr">I wrote a technote on modifying V5 Oberon for different video geometries and more memory.<div><br></div><div>It mostly summarizes what other people have done.</div><div><br></div><div>If anyone is curious it can be found at:</div><div><a href="https://github.com/io-core/technotes/blob/master/technote002.md" target="_blank">https://github.com/io-core/technotes/blob/master/technote002.md</a><br></div><div><br></div><div>The ROM offsets I used to patch the boot loader are off by one from Michael Schirl's code... FYI!</div><div><br></div><div>Best Regards,</div><div>Chuck</div><div><br></div></div></div>
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