<div dir="ltr"><div dir="ltr"><div dir="ltr"><div><div><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div><div><a target="_blank" href="mailto:rochus.keller@bluewin.ch" id="gmail-m_-7590894345021664675gmail-plusReplyChip-0" class="gmail_plusreply">@R. K.</a> <br></div>Just for the sake of clarity:<br><br></div>Hardware Compilation in that article ("<a href="http://286.ps">286.ps</a>") is a process to translate experimental subset of Oberon (Oberon-00), that only deals with boolean and integer data types for variables, and for structured constructions only the assignment, if and while.<br><a target="_blank" href="http://www.cs.inf.ethz.ch/lola/hcl/">http://www.cs.inf.ethz.ch/lola/hcl/</a><br><a target="_blank" href="http://www.cs.inf.ethz.ch/lola/hcl/HCL.tgz">http://www.cs.inf.ethz.ch/lola/hcl/HCL.tgz</a><br></div><div>That experimental small language translates to a Lo(gic)La(nguage) tree structure ("<a href="http://236.ps">236.ps</a>"), a mature educational framework for teaching classes on digital design then.<br><a target="_blank" href="http://www.cs.inf.ethz.ch/lola/lola_lang/">http://www.cs.inf.ethz.ch/lola/lola_lang/</a><br></div><div>Then with LoLa Tools you can simulate ("<a href="http://215.ps">215.ps</a>") the resulting circuit that implements your program written in Oberon-00.<br><a target="_blank" href="http://www.cs.inf.ethz.ch/lola/simulator/">http://www.cs.inf.ethz.ch/lola/simulator/</a><br><br>In summary:<br></div><div>Oberon-00 -> LoLa tree structure -> LoLa Simulation<br><br></div><div>With software Trianus and Hades and others related, also from in ETHZ, you could map graphic&manually ("<a href="http://198.ps">198.ps</a>" and others) to an FPGA of the old open structure 6000 (Xilinx, Atmel, etc.), and check if it matches to a LoLa description that you previously written as a model. Just the same method that is used today for VLSI and IC-layout. In summary:<br><br></div><div>FPGA Layout -> Layout LoLa tree = equivalent? = Description LoLa tree <- LoLa description (text)<br><br>Some references about that tools:<br><a target="_blank" href="http://www.cs.inf.ethz.ch/lola/index.html">http://www.cs.inf.ethz.ch/lola/index.html</a><br><a target="_blank" href="http://www.cs.inf.ethz.ch/lola/trianus/">http://www.cs.inf.ethz.ch/lola/trianus/</a><br><br><a target="_blank" href="ftp://ftp.inf.ethz.ch/pub/publications/tech-reports/1xx/198.ps">ftp://ftp.inf.ethz.ch/pub/publications/tech-reports/1xx/198.ps</a><br><br><a target="_blank" href="ftp://ftp.inf.ethz.ch/doc/papers/cs/FPL94.ps">ftp://ftp.inf.ethz.ch/doc/papers/cs/FPL94.ps</a><br><br><div class="gmail-m_-7590894345021664675gmail-TbwUpd"><cite class="gmail-m_-7590894345021664675gmail-iUh30"><a target="_blank" href="ftp://ftp.inf.ethz.ch/doc/papers/cs/FPL96.Trianus.ps">ftp://ftp.inf.ethz.ch/doc/papers/cs/FPL96.Trianus.ps</a><br><br></cite></div><a target="_blank" href="https://oberoncore.ru/_media/library/ludwig_hades_fast_hardware_synthesis_tools_and_a_reconfigurable_coprocessor.pdf">https://oberoncore.ru/_media/library/ludwig_hades_fast_hardware_synthesis_tools_and_a_reconfigurable_coprocessor.pdf</a><br><br></div><div><a target="_blank" href="https://www.researchgate.net/publication/221173290_FPGA_synthesis_on_the_XC6200_using_IRIS_and_TrianusHades_or_from_heaven_to_hell_and_back_again">https://www.researchgate.net/publication/221173290_FPGA_synthesis_on_the_XC6200_using_IRIS_and_TrianusHades_or_from_heaven_to_hell_and_back_again</a><br><br><cite class="gmail-m_-7590894345021664675gmail-iUh30"><a target="_blank" href="ftp://ftp-dept.inf.ethz.ch/doc/papers/cs/FPL96.Coproc.ps">ftp://ftp-dept.inf.ethz.ch/doc/papers/cs/FPL96.Coproc.ps</a></cite><br></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div><br></div>All of the software tools work in Oberon versions of around 2000's for workstation including DOS & Windows PCs. I didn't have 6000 FPGA at the time, then I only simulates with LoLa tools in Project Oberon for Windows and DOS.<br><br>In summary, LoLa-1 was not about the behavioral description of hardware but structural; that was the hardware compilation experiment with a traditional computer programming language translated to hardware. At least that's what I know about it.<br><br></div><div>Thanks to your questions I'm rediscovering all the material, I have only printed versions in my archives, till now, and now everyone of you could read too. And if any of you continue with the experiments or recreate it, please let us know!<br></div><div><br></div>Pablo Cayuela<br><br><div><br><div><div><div class="gmail_quote"><div class="gmail_attr" dir="ltr">On Sat, Mar 16, 2019 at 8:08 AM <a target="_blank" href="mailto:rochus.keller@bluewin.ch">rochus.keller@bluewin.ch</a> <<a target="_blank" href="mailto:rochus.keller@bluewin.ch">rochus.keller@bluewin.ch</a>> wrote:<br></div><blockquote style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex" class="gmail_quote">@Wojciech Skulski<br>
<br>
Thanks for the document. <br>
<br>
Here are two links that might also help to illustrate your argument:<br>
<a target="_blank" rel="noreferrer" href="https://www.vlsifacts.com/different-coding-styles-verilog-language/">https://www.vlsifacts.com/different-coding-styles-verilog-language/</a><br>
<a target="_blank" rel="noreferrer" href="https://www.researchgate.net/publication/3646848_Behavior_to_structure_using_Verilog_and_in-circuit_emulation_to_teach_how_an_algorithm_becomes_hardware">https://www.researchgate.net/publication/3646848_Behavior_to_structure_using_Verilog_and_in-circuit_emulation_to_teach_how_an_algorithm_becomes_hardware</a><br>
<br>
Here is yet another link to an article I got from Pablo which illustrates what was intended by Lola-1 (presumably in contrast to Lola-2): <a target="_blank" rel="noreferrer" href="http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.51.643">http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.51.643</a><br>
<br>
Best<br>
R. <br>
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