<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto">Rochus<div><br><blockquote type="cite"><div dir="ltr"><span>I also would like to discuss whether there is a way to avoid using a Xilinx specific module for TS() in the Verilog code generated by the Lola-2 compiler, see e.g. <a href="https://github.com/rochus-keller/Lolac/blob/1cac988503e6b081619848a1fe11b96e106e9c04/Examples/RISC5_translated/RISC5Top.v#L49">https://github.com/rochus-keller/Lolac/blob/1cac988503e6b081619848a1fe11b96e106e9c04/Examples/RISC5_translated/RISC5Top.v#L49</a></span><br></div></blockquote><div><br></div>In my point of view the Lola compiler could translate tri-state (0, 1, Z) buffers to more „standard“ Verilog.</div><div><br></div><div><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><font face="UICTFontTextStyleBody"><span style="white-space: normal; background-color: rgba(255, 255, 255, 0);"><span class="Normal-C12" style="line-height: 1.19em;">Something like:</span></span></font></pre><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><font face="UICTFontTextStyleBody"><span style="white-space: normal; background-color: rgba(255, 255, 255, 0);"><span class="Normal-C12" style="line-height: 1.19em;"><br></span></span></font></pre><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><font face="UICTFontTextStyleBody"><span style="white-space: normal; background-color: rgba(255, 255, 255, 0);"><span class="Normal-C12" style="line-height: 1.19em;">module</span><span class="Normal-C13" style="line-height: 1.19em;"> tristate_buffer(I, enable, O);</span></span></font></pre><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><font face="UICTFontTextStyleBody"><span style="white-space: normal; background-color: rgba(255, 255, 255, 0);"><span class="Normal-C14" style="line-height: 1.19em;"> input</span><span class="Normal-C13" style="line-height: 1.19em;"> I, enable;</span></span></font></pre><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><font face="UICTFontTextStyleBody"><span style="white-space: normal; background-color: rgba(255, 255, 255, 0);"><span class="Normal-C14" style="line-height: 1.19em;"> output</span><span class="Normal-C13" style="line-height: 1.19em;"> O;</span></span></font></pre><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><font face="UICTFontTextStyleBody"><span style="white-space: normal; background-color: rgba(255, 255, 255, 0);"><span class="Normal-C15" style="line-height: 1.19em;"> assign</span><span class="Normal-C13" style="line-height: 1.19em;"> O = enable ? I : 1'bz;</span></span></font></pre><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><font face="UICTFontTextStyleBody"><span style="white-space: normal; background-color: rgba(255, 255, 255, 0);">endmodule</span></font></pre><pre class="Preformatted" style="margin-left: 0em; margin-top: 0em; margin-bottom: 0em;"><br></pre></div><div>But I guess the IOBUF primitive will be much more optimized in terms of routing and timing.</div><div><br></div><div>If you have another FPGA board with another synthesizer tool, the easiest is probably to modify LSV to generate the optimized tri-state primitives for your board.</div><div><br></div><div>br</div><div>Jörg<br></div><div><br></div></body></html>