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</o:shapelayout></xml><![endif]--></head><body lang=DE-CH link="#0563C1" vlink="#954F72"><div class=WordSection1><p class=MsoNormal><span lang=EN-US>Wojtek<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>Here NW describes the CPU for a Harvard architecture (his RISC1).<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>He mentions the important detail that “adr” is stable in the second half of the cycle and “wr” has to be ored with “clk” and that the signals are active low!<o:p></o:p></span></p><p class=MsoNormal><img width=639 height=638 style='width:6.6562in;height:6.6458in' id="_x0000_i1027" src="cid:image001.jpg@01D5B74F.C92EE210"><o:p></o:p></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>And here he describes what had to be modified to cover the von Neumann architecture (his RISC2). The speed had to be reduced to 25 MHz.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><img width=632 height=523 style='width:6.5833in;height:5.4479in' id="Picture_x0020_2" src="cid:image002.jpg@01D5B74F.C92EE210"></span><span lang=EN-US><o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Jörg<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='mso-fareast-language:DE-CH'>From:</span></b><span lang=EN-US style='mso-fareast-language:DE-CH'> Oberon <oberon-bounces@lists.inf.ethz.ch> <b>On Behalf Of </b>Joerg<br><b>Sent:</b> Friday, December 20, 2019 2:45 PM<br><b>To:</b> 'ETH Oberon and related systems' <oberon@lists.inf.ethz.ch><br><b>Subject:</b> Re: [Oberon] FPGA RISC byte access<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoPlainText><span lang=EN-US>Hi Wojtek<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>I tried to just roughly dump my view of how the RISC5 CPU’s timing looks like (qualitative not quantitative)<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US><img width=636 height=266 style='width:6.625in;height:2.7708in' id="Picture_x0020_1" src="cid:image004.png@01D5B74E.026F2C30"><o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>On every positive edge of the clk, the IR (instruction register) is latched from codebus (=memory or cache if implemented).<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Decoding and execution starts.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Above, you see the timing for a register instruction: “adr” for the next cycle points to the next instruction.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>If the Decode finds LDR/STR, “adr” for the next cycle points to the memory location where the register is read from or written to. In other words LDR/STR need two cycles.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>If the Decode steps finds a multiplication/division, the CPU stalls itself as it expects the Execution lasts longer than 40 ns.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>If for some reason RISC5Top.v finds that the memory is occupied (inbus/codebus not ready) be it as VID.v needs a memory access or a cache has to be filled (if implemented), RISC5Top has the possibility to stall the CPU (stallX=1)<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>If you don’t want to stall the RISC5, fast memory is key, so the inbus/codebus is ready in time for the next cycle.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>br<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Jörg <o:p></o:p></span></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText><span lang=EN-US style='mso-fareast-language:DE-CH'>-----Original Message-----<br>From: Oberon <<a href="mailto:oberon-bounces@lists.inf.ethz.ch">oberon-bounces@lists.inf.ethz.ch</a>> On Behalf Of Skulski, Wojciech<br>Sent: Friday, December 20, 2019 2:41 PM<br>To: ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch">oberon@lists.inf.ethz.ch</a>><br>Subject: Re: [Oberon] FPGA RISC byte access</span><o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Joerg:<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>> You’re right. Would be nice [to have a data sheet -- WS]. Please remember: NWs RISC5 is not the Chip itself but the microcode defining the chip/instruction set.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Functionally it is a chip. Fact that it is soft does not change its functionality. It is as real as an ASIC would have been, if someone is not changing its Verilog.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>>The exact timings are defined by the FPGA used and the FPGA routing SW when it positions the logic elements in the FPGA.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Exact yes. Nominal no.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>> As meanwhile the RISC5 microcode was implemented on different FPGAs, you would have to measure the signal timings yourself for your FPGA.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Yes for exact, no for nominal. By "nominal" I mean the sequence of signals issued by the RISC5 chip relative to clock. For example, the chip is issuing a read strobe "rd". Then it expects to receive the data from memory. Nominal specs are saying "in the same clock cycle", "next clock cycle", "two clocks later", etc. <o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Every chip vendor provides this kind of info, usually in a form of a diagram. Take any data sheet for any memory chip (for example) and you will see such diagrams. They are needed to write the interface code.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>The PO documents describe the history of development in detail, as well as the design decisions. But the product itself is undocumented. As a designer of the interface logic I would like to know inputs, outputs, their polarity, and the nominal sequencing of the in/out wires in terms of clock cycles. This information is missing. It would be good to know in order to use this chip in other designs.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>W.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>--<o:p></o:p></p><p class=MsoPlainText><a href="mailto:Oberon@lists.inf.ethz.ch"><span lang=EN-US style='color:windowtext;text-decoration:none'>Oberon@lists.inf.ethz.ch</span></a><span lang=EN-US> mailing list for ETH Oberon and related systems </span><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon"><span lang=EN-US style='color:windowtext;text-decoration:none'>https://lists.inf.ethz.ch/mailman/listinfo/oberon</span></a><span lang=EN-US><o:p></o:p></span></p></div></body></html>