<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta name=Generator content="Microsoft Word 15 (filtered medium)"><!--[if !mso]><style>v\:* {behavior:url(#default#VML);}
o\:* {behavior:url(#default#VML);}
w\:* {behavior:url(#default#VML);}
.shape {behavior:url(#default#VML);}
</style><![endif]--><style><!--
/* Font Definitions */
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0cm;
margin-bottom:.0001pt;
font-size:11.0pt;
font-family:"Calibri",sans-serif;
mso-fareast-language:EN-US;}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:#0563C1;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:#954F72;
text-decoration:underline;}
p.MsoPlainText, li.MsoPlainText, div.MsoPlainText
{mso-style-priority:99;
mso-style-link:"Plain Text Char";
margin:0cm;
margin-bottom:.0001pt;
font-size:11.0pt;
font-family:"Calibri",sans-serif;
mso-fareast-language:EN-US;}
span.PlainTextChar
{mso-style-name:"Plain Text Char";
mso-style-priority:99;
mso-style-link:"Plain Text";
font-family:"Calibri",sans-serif;}
.MsoChpDefault
{mso-style-type:export-only;
font-family:"Calibri",sans-serif;
mso-fareast-language:EN-US;}
@page WordSection1
{size:612.0pt 792.0pt;
margin:70.85pt 70.85pt 2.0cm 70.85pt;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]--></head><body lang=DE-CH link="#0563C1" vlink="#954F72"><div class=WordSection1><p class=MsoPlainText><span lang=EN-US>Hi Wojtek<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>I tried to just roughly dump my view of how the RISC5 CPU’s timing looks like (qualitative not quantitative)<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US><img width=636 height=266 style='width:6.625in;height:2.7708in' id="Picture_x0020_1" src="cid:image001.png@01D5B744.1E0179D0"></span><span lang=EN-US><o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>On every positive edge of the clk, the IR (instruction register) is latched from codebus (=memory or cache if implemented).<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Decoding and execution starts.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Above, you see the timing for a register instruction: “adr” for the next cycle points to the next instruction.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>If the Decode finds LDR/STR, “adr” for the next cycle points to the memory location where the register is read from or written to. In other words LDR/STR need two cycles.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>If the Decode steps finds a multiplication/division, the CPU stalls itself as it expects the Execution lasts longer than 40 ns.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>If for some reason RISC5Top.v finds that the memory is occupied (inbus/codebus not ready) be it as VID.v needs a memory access or a cache has to be filled (if implemented), RISC5Top has the possibility to stall the CPU (stallX=1)<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>If you don’t want to stall the RISC5, fast memory is key, so the inbus/codebus is ready in time for the next cycle.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>br<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Jörg <o:p></o:p></span></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText><span lang=EN-US style='mso-fareast-language:DE-CH'>-----Original Message-----<br>From: Oberon <oberon-bounces@lists.inf.ethz.ch> On Behalf Of Skulski, Wojciech<br>Sent: Friday, December 20, 2019 2:41 PM<br>To: ETH Oberon and related systems <oberon@lists.inf.ethz.ch><br>Subject: Re: [Oberon] FPGA RISC byte access</span></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Joerg:<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>> You’re right. Would be nice [to have a data sheet -- WS]. Please remember: NWs RISC5 is not the Chip itself but the microcode defining the chip/instruction set.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Functionally it is a chip. Fact that it is soft does not change its functionality. It is as real as an ASIC would have been, if someone is not changing its Verilog.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>>The exact timings are defined by the FPGA used and the FPGA routing SW when it positions the logic elements in the FPGA.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Exact yes. Nominal no.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>> As meanwhile the RISC5 microcode was implemented on different FPGAs, you would have to measure the signal timings yourself for your FPGA.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Yes for exact, no for nominal. By "nominal" I mean the sequence of signals issued by the RISC5 chip relative to clock. For example, the chip is issuing a read strobe "rd". Then it expects to receive the data from memory. Nominal specs are saying "in the same clock cycle", "next clock cycle", "two clocks later", etc. <o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>Every chip vendor provides this kind of info, usually in a form of a diagram. Take any data sheet for any memory chip (for example) and you will see such diagrams. They are needed to write the interface code.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>The PO documents describe the history of development in detail, as well as the design decisions. But the product itself is undocumented. As a designer of the interface logic I would like to know inputs, outputs, their polarity, and the nominal sequencing of the in/out wires in terms of clock cycles. This information is missing. It would be good to know in order to use this chip in other designs.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>W.<o:p></o:p></p><p class=MsoPlainText><o:p> </o:p></p><p class=MsoPlainText>--<o:p></o:p></p><p class=MsoPlainText><a href="mailto:Oberon@lists.inf.ethz.ch"><span lang=EN-US style='color:windowtext;text-decoration:none'>Oberon@lists.inf.ethz.ch</span></a><span lang=EN-US> mailing list for ETH Oberon and related systems </span><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon"><span lang=EN-US style='color:windowtext;text-decoration:none'>https://lists.inf.ethz.ch/mailman/listinfo/oberon</span></a><span lang=EN-US><o:p></o:p></span></p></div></body></html>