<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto">Hi<div><br></div><div>A remark on interrupts in ProjectOberon:</div><div>The current implementation of interrupts looks to me a little bit like a quick and dirty hack or proof of concept. I don‘t find it user-friendly a programmer has to import SYSTEM and has to know the „magic“ address 4. Let me explain.<div><br></div><div>Offering interrupts to the programmer needs three parts:</div><div>- CPU support: instructions to enable/disable interrupts and return from interrupts.</div><div> DONE.</div><div>- Compiler support: PROCEDURE* is parsed and correct instructions are generated.</div><div> DONE.</div><div>- OS support: an easy to use API to use the interrupt in a program.</div><div> MISSING.</div><div><br></div><div>Of course I can provide an API myself. Eg:</div><div><br></div><div>MODULE Interrupt; (* jr/31dec19 *)</div><div> IMPORT SYSTEM, Kernel;</div><div><br></div><div> PROCEDURE* Empty; END Empty;</div><div><br></div><div> PROCEDURE Install*(handler: PROCEDURE); (* handler=NIL: deactivate interrupts *)</div><div> VAR instr: INTEGER;</div><div> BEGIN</div><div> SYSTEM.LDPSR(0);</div><div> Kernel.Install(SYSTEM.ADR(Empty), 4);</div><div> SYSTEM.GET(SYSTEM.VAL, INTEGER, handler)+4, instr);</div><div> IF instr = 0A0E00000H THEN (* valid interrupt handler *)</div><div> Kernel.Install(SYSTEM.VAL(INTEGER, handler), 4);</div><div> SYSTEM.LDPSR(1)</div><div> END</div><div> END Install;</div><div><br></div><div>BEGIN Install(NIL) END Interrupt.</div><div><br></div><div><div>For me something like the above should be part of the inner core (e.g. Kernel.Mod) or at least a module of the outer core to be provided with the standard distribution.</div></div><div>With the above API, interrupts are easily consumable (no import of SYSTEM, all the nitty gritty details hidden in Interrupt.Mod)</div><div><br></div><div><div>MODULE TestInt;</div><div>IMPORT Interrupt;</div><div>VAR led, cnt: INTEGER;</div><div>PROCEDURE* Int; (*interrupt handler called every millisecond*)</div><div> BEGIN</div><div> INC(cnt); IF cnt = 500 THEN led := 3 - led; LED(led); cnt := 0 END</div><div> END Int;</div><div>PROCEDURE On*; BEGIN Interrupt.Install(Int) END On;</div><div>PROCEDURE Off*; BEGIN Interrupt.Install(NIL) END Off;</div><div>BEGIN</div><div> led := 1; cnt := 0</div><div>END TestInt.</div></div><div><br></div><div>br</div><div>Jörg</div><div><div dir="ltr"><br><blockquote type="cite">Am 30.12.2019 um 16:12 schrieb Charles Perkins <chuck@kuracali.com>:<br><br></blockquote></div><blockquote type="cite"><div dir="ltr"><div dir="ltr">Hi Paul and Jörg,<div><br></div><div>Sometimes I am too clever for my own good. I thought I saw a way out of the name confusion. I'll make it clear that RISC5 is the correct name for the architecture. Also, I missed the CPU version bits in the emulator -- I will have to make sure the SYSTEM.H code works too... after I correct DIV for negative operands and finish floating point! </div><div><br></div><div>Of course this is just another emulator and the Oberon community already has plenty of those but I wanted to work with just one emulation platform across several porting efforts, and QEMU is to me the obvious choice. And as a side benefit it seems quite fast, comparatively. </div><div><br></div><div>Cheers,</div><div>Chuck</div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Dec 30, 2019 at 1:43 AM Jörg <<a href="mailto:joerg.straube@iaeth.ch">joerg.straube@iaeth.ch</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hi<br>
<br>
You can ask the RISC processor to reveal its version with this code<br>
<br>
cpu := SYSTEM.H(2019) MOD 80H;<br>
IF cpu = 53H THEN (* RISC5: with interrupts + floating-point, 31.8.2018 *)<br>
ELSIF cpu = 54H THEN (* RISC5a: no interrupts, no floating-point, 1.9.2018*)<br>
ELSIF cpu = A0H THEN (* RISC0, 26.12.2013 *)<br>
END;<br>
<br>
br<br>
Jörg<br>
<br>
Am 30.12.19, 09:56 schrieb "Oberon im Auftrag von Paul Reed" <<a href="mailto:oberon-bounces@lists.inf.ethz.ch" target="_blank">oberon-bounces@lists.inf.ethz.ch</a> im Auftrag von <a href="mailto:paulreed@paddedcell.com" target="_blank">paulreed@paddedcell.com</a>>:<br>
<br>
Hi Chuck,<br>
<br>
> ...the target is named risc6<br>
> to avoid confusion with the already existing riscv target in qemu and<br>
> because in one communication (An Update of the RISC5 Implementation<br>
> [1]) Professor Wirth defines module RISC6 to introduce interrupts into<br>
> the architecture.<br>
<br>
Sorry I think that's a mis-print since it's the only occurrence, I'm <br>
pretty sure the intention was to keep it as RISC5. Apologies for any <br>
confusion.<br>
<br>
As it happens most of the stuff for interrupts was there originally <br>
anyway before the update, especially in the compiler. The RISC5 source <br>
on Prof. Wirth's site definitely contains the interrupt code now. <br>
There's also a RISC5a version, without interrupts and without <br>
floating-point.<br>
<br>
Cheers,<br>
Paul<br>
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