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<div class="moz-cite-prefix">Correction:</div>
<div class="moz-cite-prefix"> 8 bpp needs 0.75 MB memory, 16 bpp
needs 1.5 MB memory for display buffer <br>
</div>
<div class="moz-cite-prefix"><br>
</div>
<div class="moz-cite-prefix">On 5/27/2020 3:50 PM, Magnus Karlsson
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:af111d4b-b57f-9599-19d2-ecdcf62144fc@saanlima.com">I
have made updates to the code on github with the following
changes:
<br>
<br>
* The code now has it's own repository with a master branch and
two versions with color display added
<br>
* The mono display buffer in BRAM is now 160 KB, big enough for a
1440x900 display
<br>
* The CPU clock is now coming from the memory controller PLL,
leaving the video PLL free to implement any frequency needed by
the video controller
<br>
* The cache is now 64KB (2-way, 128-set, 256 bytes/cache line) to
make room for the larger mono display buffer
<br>
* The color version have 8 bpp or 16 bpp color video added in
parallel with the mono display. <i> 8 bpp needs 0.75 MB memory, 16
bpp needs 1.5 MB memory for display buffer
</i><br>
* The color buffer can be at any place in the 15.75 MB lpddr
memory space (aligned to 16 bytes) controlled by a color buffer
address register
<br>
* When using color display the cache needs to be flushed. There
are several ways to flush the cache - on demand by software, on
every vsync and using auto-flush where a cache line is flushed
every 1024 CPU clocks.
<br>
* The selection between mono display and color display is via a
register bit.
<br>
<br>
Jörg Straube have successfully shown the code working in both
1440x900 mono display mode and 8 bpp color display mode.
<br>
<br>
<a class="moz-txt-link-freetext" href="https://github.com/Saanlima/RISC5Verilog_lpddr">https://github.com/Saanlima/RISC5Verilog_lpddr</a>
<br>
<br>
Cheers,
<br>
Magnus
<br>
<br>
On 5/15/2020 7:53 AM, Magnus Karlsson wrote:
<br>
<blockquote type="cite">The project have been updated at
<a class="moz-txt-link-freetext" href="https://github.com/Saanlima/Pipistrello/tree/master/Projects/Oberon_lpddr">https://github.com/Saanlima/Pipistrello/tree/master/Projects/Oberon_lpddr</a><br>
This version is based on the current RISC5 verilog code (dated
11.12.2018).
<br>
<br>
System info:
<br>
Cache size: 128 KB (2-way 256-set).
<br>
Cached area: lower 15.75 MB of the RISC5 memory map is mapped to
cache/lpddr memory.
<br>
The non-cached area (top 256 KB of the RISC5 memory map) is used
for I/O (top 4KB), boot prom (next 4KB), then a free 248 KB area
where the video display buffer can be relocated .
<br>
Video buffer is in BRAM and is located at the default place at
power up but can be relocated anywhere in the memory map by
simply writing to a new 24-bit video base register.
<br>
Since the video frame buffer is in non-cached BRAM there is no
need to flush the cache, which btw uses write-back policy.
<br>
The system will be slowed down by cache misses but there is
about 11% gain by having the video buffer in BRAM (no cpu stalls
due to video controller memory access).
<br>
<br>
Magnus
<br>
</blockquote>
<br>
--
<br>
<a class="moz-txt-link-abbreviated" href="mailto:Oberon@lists.inf.ethz.ch">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related
systems
<br>
<a class="moz-txt-link-freetext" href="https://lists.inf.ethz.ch/mailman/listinfo/oberon">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a>
<br>
</blockquote>
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