<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""> > ><i class="">Add the small number of “Original Oberon-2” features such as LOOP, EXIT</i></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""> > ><i class="">and RETURN to the compiler just to *initially* speed up the porting effort of</i></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""> > ><i class="">V4. But *eventually* eliminate those constructs *on* the then-ported system.</i></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""> > ><i class="">The advantage would be that one would not need to also deal with porting</i></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""> > ><i class="">complex, nested LOOP statements initially, thereby reducing risk of errors..</i></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69); min-height: 14px;" class=""> ></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""> > Sounds like a plan. A dream would be to have a V4 successor named V6</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""> > replacing V4 under Windows and Linux, and also running on the FPGA.</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""><br class=""></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class="">An alternative approach would be to *first* rewrite V4 under V4 itself to "clean</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class="">it up", as you had suggested in a previous message, i.e. first eliminate LOOP,</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class="">EXIT and RETURN *under V4*, step by step, while keeping V4 running. Then</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class="">compile for FPGA (either on V4 using a cross-compiler or on the FPGA itself).</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""><br class=""></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class="">That way, one doesn’t need to amend the Oberon-07 compiler.</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""><br class=""></div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class="">PS: Personally, I would be more interested in V4 für RISC-V, where</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class="">Extended Oberon also runs (but with no memory limitations).</div><div style="margin: 0px; line-height: normal; color: rgb(69, 69, 69);" class=""><br class=""></div></body></html>