<div dir="ltr">I intend to leave .rsc alone. I've added a switch to ORP for cross compilation to other architectures. Intel binaries end up with the .i64 extension, Arm gets .a64 (or .a32 for 32-bit arm) and risc-v gets .v64 (or .v32 for 32-bit risc-v.) The file extension choices were arbitrary.<div><br></div><div>With this convention a single file system may potentially be booted on any of the above architectures. </div><div><br></div><div>For development I already have a QEMU setup that loads and begins executing a Oberon-produced code for x86_64, aarch64, arm32, rv64, and rv32. I also have a QEMU RISC5 emulation that boots all the way to graphics and command execution.</div><div><br></div><div>The Oberon-produced code for the other architectures is currently nothing more than a jump over global variables and then an infinite loop. Next up: serial output of a test string!</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Jan 15, 2021 at 3:57 PM Joerg <<a href="mailto:joerg.straube@iaeth.ch">joerg.straube@iaeth.ch</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div lang="DE-CH" style="overflow-wrap: break-word;"><div class="gmail-m_-2791413851320478921WordSection1"><p class="MsoNormal"><span lang="EN-US">I guess you will stick to the RISC5 instruction set. You have to decide, whether you want to store the rsc files in 32bit (as today) or will store them in 64 bits as well (although only 32 bits are used). Your decision has an influence on the bootloader, compiler and the loader.<u></u><u></u></span></p><p class="MsoNormal"><span lang="EN-US">br<u></u><u></u></span></p><p class="MsoNormal"><span lang="EN-US">Jörg<u></u><u></u></span></p><p class="MsoNormal"><span lang="EN-US"><u></u> <u></u></span></p><div style="border-right:none;border-bottom:none;border-left:none;border-top:1pt solid rgb(181,196,223);padding:3pt 0cm 0cm"><p class="MsoNormal"><b><span style="font-size:12pt;color:black">Von: </span></b><span style="font-size:12pt;color:black">Oberon <<a href="mailto:oberon-bounces@lists.inf.ethz.ch" target="_blank">oberon-bounces@lists.inf.ethz.ch</a>> im Auftrag von Charles Perkins <<a href="mailto:chuck@kuracali.com" target="_blank">chuck@kuracali.com</a>><br><b>Antworten an: </b>ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch" target="_blank">oberon@lists.inf.ethz.ch</a>><br><b>Datum: </b>Samstag, 16. Januar 2021 um 00:32<br><b>An: </b>ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch" target="_blank">oberon@lists.inf.ethz.ch</a>><br><b>Betreff: </b>Re: [Oberon] Re (2): V4, 64 bit version;<u></u><u></u></span></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal">In my case the interest is being able to use the full capabilities of a 64-bit platform, including addressing more than 4 gigabytes of RAM.<u></u><u></u></p><div><p class="MsoNormal"><u></u> <u></u></p></div><div><p class="MsoNormal"><u></u> <u></u></p></div></div><p class="MsoNormal"><u></u> <u></u></p><div><div><p class="MsoNormal">On Fri, Jan 15, 2021 at 2:37 PM <<a href="mailto:peter@easthope.ca" target="_blank">peter@easthope.ca</a>> wrote:<u></u><u></u></p></div><blockquote style="border-top:none;border-right:none;border-bottom:none;border-left:1pt solid rgb(204,204,204);padding:0cm 0cm 0cm 6pt;margin-left:4.8pt;margin-right:0cm"><p class="MsoNormal">From: Charles Perkins <<a href="mailto:chuck@kuracali.com" target="_blank">chuck@kuracali.com</a>><br>Date: Fri, 15 Jan 2021 13:17:03 -0800<br>> On review of the source, I see that LONGREAL is currently aliased to REAL<br>> in ORB, suggesting that REAL may stay 32-bit and LONGREAL would be 64-bit.<br>> Would the same be done for SET, introducing LONGSET perhaps?<br><br>From the new Project Oberon book I had the impression that the gain of <br>one type rather than two outweighed the loss of storing some numbers <br>in capacities larger than necessary.<br><br>If so, wouldn't any machine have only REAL, according to hardware <br>capability, whether 32 bits or 64 bits or 128 bits?<br><br>What are the requirements motivating interest in 64 bits? Numerical <br>modeling?<br><br>Thanks, ... P. L.<br><br>-- <br>Tel: +1 604 670 0140 Bcc: peter at easthope. ca<br><br>--<br><a href="mailto:Oberon@lists.inf.ethz.ch" target="_blank">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related systems<br><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a><u></u><u></u></p></blockquote></div><p class="MsoNormal">-- <a href="mailto:Oberon@lists.inf.ethz.ch" target="_blank">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related systems <a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a> <u></u><u></u></p></div></div>
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