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--></style></head><body lang=DE-CH link=blue vlink=purple style='word-wrap:break-word'><div class=WordSection1><p class=MsoNormal><span style='mso-fareast-language:EN-US'>Hi Jeff<o:p></o:p></span></p><p class=MsoNormal><span style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>The interrupt signal is handed over by the HW to the RISC5 CPU in RISC5Top.v.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>The interrupt signal in the CPU is called .irq, and the current RISC5Top.v hands over periodic interrupts with the Verilog code below<o:p></o:p></span></p><pre><span lang=EN-US>RISC5 riscx(.clk(clk), .rst(rst), <b><span style='color:red'>.irq(limit),</span></b><o:p></o:p></span></pre><p class=MsoNormal><span lang=EN-US style='font-size:10.0pt;font-family:"Courier New"'> .rd(rd), .wr(wr), .ben(ben), .stallX(vidreq),<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:10.0pt;font-family:"Courier New"'> </span><span style='font-size:10.0pt;font-family:"Courier New"'>.adr(adr), .codebus(codebus), .inbus(inbus),<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Courier New"'> .outbus(outbus));<o:p></o:p></span></p><pre><o:p> </o:p></pre><pre>assign limit = (cnt0 == 24999);<o:p></o:p></pre><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>But you are totally free to set the CPU’s .irq signal on other HW conditions, e.g. a packet on the Ethernet board arrived or the temperature sensor says the meat is tender.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>Below I attached an older mail on an “simple” API to facilitate programming with interrupts. Instead of Kernel.Install you would call Interrupt.Install to install the interrupt handler.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>br<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'>Jörg<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='mso-fareast-language:EN-US'><o:p> </o:p></span></p><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span style='font-size:12.0pt;color:black'>Von: </span></b><span style='font-size:12.0pt;color:black'>Oberon <oberon-bounces@lists.inf.ethz.ch> im Auftrag von Jeff Maggio <jmaggio14@gmail.com><br><b>Antworten an: </b>ETH Oberon and related systems <oberon@lists.inf.ethz.ch><br><b>Datum: </b>Donnerstag, 6. Mai 2021 um 13:44<br><b>An: </b><oberon@lists.inf.ethz.ch><br><b>Betreff: </b>[Oberon] Stimulus driven interrupts?<o:p></o:p></span></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><div><p class=MsoNormal>Hi all,<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I'm using Oberon on an embedded RISC5 system, and am able to modify both firmware and software. <o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>In this Oberon-1 paper (<b><a href="http://norayr.am/papers/WirthTasksVersusThreads.pdf">http://norayr.am/papers/WirthTasksVersusThreads.pdf</a></b>) from 1996, Wirth discusses a method of "real-time tasks". <b>(Page 10)</b>. In which I believe interrupt handlers installed with <b>Kernel.Install(Handler, N)</b> are triggered when a device or buffer is updated? The details are unclear in the paper. <o:p></o:p></p><div><p class=MsoNormal><br>I see that <b>Kernel.Install</b> still exists in the RISC5 source. Can this method still be used for "real-time tasks" in which a procedure is run when an external stimulus changes? So far all the interrupt examples I've seen make use of interrupts triggered periodically by the millisecond timer.<o:p></o:p></p></div><div><p class=MsoNormal><br>My end goal is to trigger an interrupt (from firmware or otherwise) in reaction to stimulus without having to wait for the millisecond timer<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>best,<o:p></o:p></p></div><div><p class=MsoNormal>Jeff<o:p></o:p></p></div></div><p class=MsoNormal>-- Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems https://lists.inf.ethz.ch/mailman/listinfo/oberon <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>. . . . . . <o:p></o:p></p><p class=MsoNormal><span lang=EN-US style='font-size:13.5pt;font-family:"-webkit-standard",serif;color:black'>Hi</span><span lang=EN-US><o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>A remark on interrupts in ProjectOberon:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>The current implementation of interrupts looks to me a little bit like a quick and dirty hack or proof of concept. I don‘t find it user-friendly a programmer has to import SYSTEM and has to know the „magic“ address 4. Let me explain.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Offering interrupts to the programmer needs three parts:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>- CPU support: instructions to enable/disable interrupts and return from interrupts.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> DONE.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>- Compiler support: PROCEDURE* is parsed and correct instructions are generated.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> DONE.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>- OS support: an easy to use API to use the interrupt in a program.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> MISSING.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Of course I can provide an API myself. Eg:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>MODULE Interrupt; (* jr/31dec19 *)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> IMPORT SYSTEM, Kernel;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> PROCEDURE* Empty; END Empty;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> PROCEDURE Install*(handler: PROCEDURE); (* handler=NIL: deactivate interrupts *)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> VAR instr: INTEGER;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> BEGIN<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> SYSTEM.LDPSR(0);<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> Kernel.Install(SYSTEM.ADR(Empty), 4);<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> SYSTEM.GET(SYSTEM.VAL, INTEGER, handler)+4, instr);<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> IF instr = 0A0E00000H THEN (* valid interrupt handler *)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> </span><span style='font-family:"-webkit-standard",serif;color:black'>Kernel.Install(SYSTEM.VAL(INTEGER, handler), 4);<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"-webkit-standard",serif;color:black'> </span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>SYSTEM.LDPSR(1)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> END<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> END Install;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>BEGIN Install(NIL) END Interrupt.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>For me something like the above should be part of the inner core (e.g. Kernel.Mod) or at least a module of the outer core to be provided with the standard distribution.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>With the above API, interrupts are easily consumable (no import of SYSTEM, all the nitty gritty details hidden in Interrupt.Mod)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>MODULE TestInt;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>IMPORT Interrupt;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>VAR led, cnt: INTEGER;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>PROCEDURE* Int; (*interrupt handler called every millisecond*)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> BEGIN<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> INC(cnt); IF cnt = 500 THEN led := 3 - led; LED(led); cnt := 0 END<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> END Int;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>PROCEDURE On*; BEGIN Interrupt.Install(Int) END On;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>PROCEDURE Off*; BEGIN Interrupt.Install(NIL) END Off;<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>BEGIN<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> led := 1; cnt := 0<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>END TestInt.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"-webkit-standard",serif;color:black'>br<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"-webkit-standard",serif;color:black'>Jörg<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"-webkit-standard",serif;color:black'><br><br><o:p></o:p></span></p><p class=MsoNormal style='margin-bottom:12.0pt'><span style='font-family:"-webkit-standard",serif;color:black'>Am 30.12.2019 um 16:12 schrieb Charles Perkins <<a href="mailto:chuck@kuracali.com">chuck@kuracali.com</a>>:<o:p></o:p></span></p><p class=MsoNormal><span style='color:black'></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Hi Paul and Jörg,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Sometimes I am too clever for my own good. I thought I saw a way out of the name confusion. I'll make it clear that RISC5 is the correct name for the architecture. Also, I missed the CPU version bits in the emulator -- I will have to make sure the SYSTEM.H code works too... after I correct DIV for negative operands and finish floating point! <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Of course this is just another emulator and the Oberon community already has plenty of those but I wanted to work with just one emulation platform across several porting efforts, and QEMU is to me the obvious choice. And as a side benefit it seems quite fast, comparatively. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Cheers,<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Chuck<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>On Mon, Dec 30, 2019 at 1:43 AM Jörg <</span><span style='font-family:"-webkit-standard",serif;color:black'><a href="mailto:joerg.straube@iaeth.ch"><span lang=EN-US>joerg.straube@iaeth.ch</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>> wrote:<o:p></o:p></span></p><p class=MsoNormal style='margin-left:40.8pt'><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Hi<br><br>You can ask the RISC processor to reveal its version with this code<br><br> cpu := SYSTEM.H(2019) MOD 80H;<br> IF cpu = 53H THEN (* RISC5: with interrupts + floating-point, 31.8.2018 *)<br> ELSIF cpu = 54H THEN (* RISC5a: no interrupts, no floating-point, 1.9.2018*)<br> ELSIF cpu = A0H THEN (* RISC0, 26.12.2013 *)<br> END;<br><br>br<br>Jörg<br><br></span><span style='color:black'></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>Am 30.12.19, 09:56 schrieb "Oberon im Auftrag von Paul Reed" <</span><span style='font-family:"-webkit-standard",serif;color:black'><a href="mailto:oberon-bounces@lists.inf.ethz.ch" target="_blank"><span lang=EN-US>oberon-bounces@lists.inf.ethz.ch</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> im Auftrag von </span><span style='font-family:"-webkit-standard",serif;color:black'><a href="mailto:paulreed@paddedcell.com" target="_blank"><span lang=EN-US>paulreed@paddedcell.com</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>>:<br><br> Hi Chuck,<br><br> > ...the target is named risc6<br> > to avoid confusion with the already existing riscv target in qemu and<br> > because in one communication (An Update of the RISC5 Implementation<br> > [1]) Professor Wirth defines module RISC6 to introduce interrupts into<br> > the architecture.<br><br> Sorry I think that's a mis-print since it's the only occurrence, I'm <br> pretty sure the intention was to keep it as RISC5. Apologies for any <br> confusion.<br><br> As it happens most of the stuff for interrupts was there originally <br> anyway before the update, especially in the compiler. The RISC5 source <br> on Prof. Wirth's site definitely contains the interrupt code now. <br> There's also a RISC5a version, without interrupts and without <br> floating-point.<br><br> Cheers,<br> Paul<br> --<br> </span><span style='font-family:"-webkit-standard",serif;color:black'><a href="mailto:Oberon@lists.inf.ethz.ch" target="_blank"><span lang=EN-US>Oberon@lists.inf.ethz.ch</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> mailing list for ETH Oberon and related systems<br> </span><span style='font-family:"-webkit-standard",serif;color:black'><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank"><span lang=EN-US>https://lists.inf.ethz.ch/mailman/listinfo/oberon</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><br><br><br><br>--<br></span><span style='font-family:"-webkit-standard",serif;color:black'><a href="mailto:Oberon@lists.inf.ethz.ch" target="_blank"><span lang=EN-US>Oberon@lists.inf.ethz.ch</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> mailing list for ETH Oberon and related systems<br></span><span style='font-family:"-webkit-standard",serif;color:black'><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" target="_blank"><span lang=EN-US>https://lists.inf.ethz.ch/mailman/listinfo/oberon</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'>--<br></span><span style='font-family:"-webkit-standard",serif;color:black'><a href="mailto:Oberon@lists.inf.ethz.ch"><span lang=EN-US>Oberon@lists.inf.ethz.ch</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'> mailing list for ETH Oberon and related systems<br></span><span style='font-family:"-webkit-standard",serif;color:black'><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon"><span lang=EN-US>https://lists.inf.ethz.ch/mailman/listinfo/oberon</span></a></span><span lang=EN-US style='font-family:"-webkit-standard",serif;color:black'><o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US style='font-size:13.5pt;font-family:"-webkit-standard",serif;color:black'>-- </span><a href="mailto:Oberon@lists.inf.ethz.ch"><span lang=EN-US style='font-family:"-webkit-standard",serif'>Oberon@lists.inf.ethz.ch</span></a><span lang=EN-US style='font-size:13.5pt;font-family:"-webkit-standard",serif;color:black'> mailing list for ETH Oberon and related systems </span><a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon"><span lang=EN-US style='font-family:"-webkit-standard",serif'>https://lists.inf.ethz.ch/mailman/listinfo/oberon</span></a><span lang=EN-US><o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p></div></body></html>