<div dir="ltr"><div dir="ltr">Ah, I didn't think to look at the source code on the site which would have been the last word.</div><div dir="ltr"> Many thanks.</div><div dir="ltr"><br clear="all"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div>All the best.</div><div><br></div><div>John<br></div><div><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div><br></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, 28 Mar 2022 at 11:00, <<a href="mailto:oberon-request@lists.inf.ethz.ch">oberon-request@lists.inf.ethz.ch</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Send Oberon mailing list submissions to<br>
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Today's Topics:<br>
<br>
1. Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a> (John Stout)<br>
2. Re: Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a> (Chris Burrows)<br>
3. Re: Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a> (Joerg)<br>
4. Re: Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a> (Chris Burrows)<br>
<br>
<br>
----------------------------------------------------------------------<br>
<br>
Message: 1<br>
Date: Sun, 27 Mar 2022 11:07:43 +0000<br>
From: John Stout <<a href="mailto:cuspcomputers@gmail.com" target="_blank">cuspcomputers@gmail.com</a>><br>
To: <a href="mailto:oberon@lists.inf.ethz.ch" target="_blank">oberon@lists.inf.ethz.ch</a><br>
Subject: [Oberon] Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a><br>
Message-ID:<br>
<<a href="mailto:CAE7M_X1Z_QJpjVft%2BpGexpLpaq7FggUYgJNA4YfWtv4zHwLanA@mail.gmail.com" target="_blank">CAE7M_X1Z_QJpjVft+pGexpLpaq7FggUYgJNA4YfWtv4zHwLanA@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
Hello everyone<br>
<br>
I'm working on a compiler and emulation of the RISC processor detailed in<br>
the latest (?) edition of Compiler Construction by Professor Wirth<br>
from CompilerConstruction1.pdf<br>
(<a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a>)<br>
<<a href="http://www.projectoberon.net/wirth/CompilerConstruction/CompilerConstruction.pdf" rel="noreferrer" target="_blank">http://www.projectoberon.net/wirth/CompilerConstruction/CompilerConstruction.pdf</a>><br>
.<br>
<br>
I can't follow the Oberon code for the emulator in section 9.5 in the<br>
section handling memory instructions, which differs from Peter De Wachter's<br>
Oberon RISC emulator at <a href="https://github.com/pdewacht/oberon-risc-emu.git" rel="noreferrer" target="_blank">https://github.com/pdewacht/oberon-risc-emu.git</a><br>
<br>
In Compiler Construction, once an instruction has been decoded as a memory<br>
instruction the address is calculated using<br>
<br>
adr := (R[b] + IR MOD 100000H) DIV 4;<br>
<br>
which (apart from the DIV 4) agrees with the code in oberon-risc-emu (which<br>
also sign extends the offset before adding it).<br>
<br>
If adr >= 0 then a load is carried out, and the N and Z flags set depending<br>
on the value loaded.<br>
However (and this is the bit I don't understand) if adr < 0 then a store is<br>
carried out, whereas in oberon-risc-emu u bit of the instruction is checked<br>
and if 0 a load is carried out and if 1 a store is carried out.<br>
<br>
Since I know oberon-risc-emu works, and that agrees with the settings for<br>
the u and v bits in Compiler Construction then I assume that must be the<br>
correct implementation, but is there an error in Compiler Construction or<br>
am I missing something very simple?<br>
<br>
All the best.<br>
<br>
John Stout<br>
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<br>
Message: 2<br>
Date: Sun, 27 Mar 2022 22:40:38 +1030<br>
From: Chris Burrows <<a href="mailto:cfbsoftware@gmail.com" target="_blank">cfbsoftware@gmail.com</a>><br>
To: ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch" target="_blank">oberon@lists.inf.ethz.ch</a>><br>
Subject: Re: [Oberon] Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a><br>
Message-ID:<br>
<CALmD50XNnbeRmA=vEoW_5WieKD=<a href="mailto:3u3mXoNy9CW4aq0c%2BsS6rUw@mail.gmail.com" target="_blank">3u3mXoNy9CW4aq0c+sS6rUw@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
On Sun, Mar 27, 2022 at 9:38 PM John Stout <<a href="mailto:cuspcomputers@gmail.com" target="_blank">cuspcomputers@gmail.com</a>> wrote:<br>
<br>
> Hello everyone<br>
><br>
> I'm working on a compiler and emulation of the RISC processor detailed in<br>
> the latest (?) edition of Compiler Construction by Professor Wirth from CompilerConstruction1.pdf<br>
> (<a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a>)<br>
> <<a href="http://www.projectoberon.net/wirth/CompilerConstruction/CompilerConstruction.pdf" rel="noreferrer" target="_blank">http://www.projectoberon.net/wirth/CompilerConstruction/CompilerConstruction.pdf</a>><br>
> .<br>
><br>
> I can't follow the Oberon code for the emulator in section 9.5 in the<br>
> section handling memory instructions, which differs from Peter De Wachter's<br>
> Oberon RISC emulator at <a href="https://github.com/pdewacht/oberon-risc-emu.git" rel="noreferrer" target="_blank">https://github.com/pdewacht/oberon-risc-emu.git</a><br>
><br>
> In Compiler Construction, once an instruction has been decoded as a memory<br>
> instruction the address is calculated using<br>
><br>
> adr := (R[b] + IR MOD 100000H) DIV 4;<br>
><br>
> which (apart from the DIV 4) agrees with the code in oberon-risc-emu<br>
> (which also sign extends the offset before adding it).<br>
><br>
> If adr >= 0 then a load is carried out, and the N and Z flags set<br>
> depending on the value loaded.<br>
> However (and this is the bit I don't understand) if adr < 0 then a store<br>
> is carried out, whereas in oberon-risc-emu u bit of the instruction is<br>
> checked and if 0 a load is carried out and if 1 a store is carried out.<br>
><br>
> Since I know oberon-risc-emu works, and that agrees with the settings for<br>
> the u and v bits in Compiler Construction then I assume that must be the<br>
> correct implementation, but is there an error in Compiler Construction or<br>
> am I missing something very simple?<br>
><br>
> All the best.<br>
><br>
> John Stout<br>
><br>
<br>
Have a closer look. In Compiler Construction the test for load / store is<br>
NOT based on the sign of adr, it is based on one of the following<br>
equivalent tests:<br>
<br>
IF ~ODD(IR DIV 20000000H) (* in the book *)<br>
<br>
or<br>
<br>
IF ~ODD(ASH(IR, -29)) (* in the accompanying source code *)<br>
<br>
--<br>
Regards,<br>
Chris Burrows<br>
CFB Software<br>
<a href="https://www.astrobe.com/RISC5" rel="noreferrer" target="_blank">https://www.astrobe.com/RISC5</a><br>
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<br>
------------------------------<br>
<br>
Message: 3<br>
Date: Sun, 27 Mar 2022 14:48:04 +0200<br>
From: Joerg <<a href="mailto:joerg.straube@iaeth.ch" target="_blank">joerg.straube@iaeth.ch</a>><br>
To: ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch" target="_blank">oberon@lists.inf.ethz.ch</a>><br>
Subject: Re: [Oberon] Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a><br>
Message-ID: <<a href="mailto:E733A707-C6CA-46FC-A43A-F2CBB38B36BF@iaeth.ch" target="_blank">E733A707-C6CA-46FC-A43A-F2CBB38B36BF@iaeth.ch</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
John<br>
<br>
there is indeed an error in chapter 9.5 of the pdf you linked.<br>
<br>
If you read bullet 3 in the intro to chapter 9.5 a distinction of adr>= 0 and adr<0 is mentioned for the memory mapped IO. But as mentioned in the intro, memory mapped IO is not implemented. For a fully working emulator you will need this IF adr>=0 and IF adr<0.<br>
But for this reduced mini emulator code in chapter 9.5, this IF is wrong (most probably a leftover of the full code). Take the sample code Chris provided.<br>
<br>
br<br>
J?rg<br>
<br>
> Am 27.03.2022 um 14:11 schrieb Chris Burrows <<a href="mailto:cfbsoftware@gmail.com" target="_blank">cfbsoftware@gmail.com</a>>:<br>
> <br>
> ?<br>
>> On Sun, Mar 27, 2022 at 9:38 PM John Stout <<a href="mailto:cuspcomputers@gmail.com" target="_blank">cuspcomputers@gmail.com</a>> wrote:<br>
> <br>
>> Hello everyone<br>
>> <br>
>> I'm working on a compiler and emulation of the RISC processor detailed in the latest (?) edition of Compiler Construction by Professor Wirth from CompilerConstruction1.pdf (<a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a>).<br>
>> <br>
>> I can't follow the Oberon code for the emulator in section 9.5 in the section handling memory instructions, which differs from Peter De Wachter's Oberon RISC emulator at <a href="https://github.com/pdewacht/oberon-risc-emu.git" rel="noreferrer" target="_blank">https://github.com/pdewacht/oberon-risc-emu.git</a> <br>
>> <br>
>> In Compiler Construction, once an instruction has been decoded as a memory instruction the address is calculated using<br>
>> <br>
>> adr := (R[b] + IR MOD 100000H) DIV 4;<br>
>> <br>
>> which (apart from the DIV 4) agrees with the code in oberon-risc-emu (which also sign extends the offset before adding it).<br>
>> <br>
>> If adr >= 0 then a load is carried out, and the N and Z flags set depending on the value loaded.<br>
>> However (and this is the bit I don't understand) if adr < 0 then a store is carried out, whereas in oberon-risc-emu u bit of the instruction is checked and if 0 a load is carried out and if 1 a store is carried out.<br>
>> <br>
>> Since I know oberon-risc-emu works, and that agrees with the settings for the u and v bits in Compiler Construction then I assume that must be the correct implementation, but is there an error in Compiler Construction or am I missing something very simple?<br>
>> <br>
>> All the best.<br>
>> <br>
>> John Stout<br>
> <br>
> Have a closer look. In Compiler Construction the test for load / store is NOT based on the sign of adr, it is based on one of the following equivalent tests:<br>
> <br>
> IF ~ODD(IR DIV 20000000H) (* in the book *)<br>
> <br>
> or<br>
> <br>
> IF ~ODD(ASH(IR, -29)) (* in the accompanying source code *)<br>
> <br>
> --<br>
> Regards,<br>
> Chris Burrows<br>
> CFB Software<br>
> <a href="https://www.astrobe.com/RISC5" rel="noreferrer" target="_blank">https://www.astrobe.com/RISC5</a><br>
> <br>
> --<br>
> <a href="mailto:Oberon@lists.inf.ethz.ch" target="_blank">Oberon@lists.inf.ethz.ch</a> mailing list for ETH Oberon and related systems<br>
> <a href="https://lists.inf.ethz.ch/mailman/listinfo/oberon" rel="noreferrer" target="_blank">https://lists.inf.ethz.ch/mailman/listinfo/oberon</a><br>
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<br>
------------------------------<br>
<br>
Message: 4<br>
Date: Mon, 28 Mar 2022 09:26:02 +1030<br>
From: Chris Burrows <<a href="mailto:cfbsoftware@gmail.com" target="_blank">cfbsoftware@gmail.com</a>><br>
To: ETH Oberon and related systems <<a href="mailto:oberon@lists.inf.ethz.ch" target="_blank">oberon@lists.inf.ethz.ch</a>><br>
Subject: Re: [Oberon] Compiler Construction on <a href="http://projectoberon.net" rel="noreferrer" target="_blank">projectoberon.net</a><br>
Message-ID:<br>
<<a href="mailto:CALmD50U%2BmHAZ3OLZJZkM4F6ChFOss9yVN9ZSdPfeL-K4afoAyg@mail.gmail.com" target="_blank">CALmD50U+mHAZ3OLZJZkM4F6ChFOss9yVN9ZSdPfeL-K4afoAyg@mail.gmail.com</a>><br>
Content-Type: text/plain; charset="utf-8"<br>
<br>
On Sun, Mar 27, 2022 at 11:18 PM Joerg <<a href="mailto:joerg.straube@iaeth.ch" target="_blank">joerg.straube@iaeth.ch</a>> wrote:<br>
<br>
> John<br>
><br>
> there is indeed an error in chapter 9.5 of the pdf you linked.<br>
><br>
> If you read bullet 3 in the intro to chapter 9.5 a distinction of adr>= 0<br>
> and adr<0 is mentioned for the memory mapped IO. But as mentioned in the<br>
> intro, memory mapped IO is not implemented. For a fully working emulator<br>
> you will need this IF adr>=0 and IF adr<0.<br>
> But for this reduced mini emulator code in chapter 9.5, this IF is wrong<br>
> (most probably a leftover of the full code). Take the sample code Chris<br>
> provided.<br>
><br>
> br<br>
> J?rg<br>
><br>
<br>
Thanks J?rg.<br>
<br>
The complete sample code that I was referring to is the file RISC.Mod on<br>
Prof Wirth's site:<br>
<br>
<a href="http://people.inf.ethz.ch/wirth/CompilerConstruction/index.html" rel="noreferrer" target="_blank">http://people.inf.ethz.ch/wirth/CompilerConstruction/index.html</a><br>
<br>
The sample code that I quoted from the book was mistakenly taken from the<br>
earlier (2013) revision of the book that I have on my computer rather than<br>
the updated (2017) version on the website. I apologise for any confusion,<br>
<br>
--<br>
Regards,<br>
Chris Burrows<br>
CFB Software<br>
<a href="https://www.astrobe.com/RISC5" rel="noreferrer" target="_blank">https://www.astrobe.com/RISC5</a><br>
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End of Oberon Digest, Vol 214, Issue 12<br>
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</blockquote></div></div>