<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto">Woytek<div><br></div><div>Do you know this?<div><a href="https://people.inf.ethz.ch/wirth/Lola/Sources/RISC5.Lola.txt">https://people.inf.ethz.ch/wirth/Lola/Sources/RISC5.Lola.txt</a><br><br><div dir="ltr">Br Jörg</div><div dir="ltr"><br><blockquote type="cite">Am 12.05.2022 um 22:29 schrieb Skulski, Wojciech <skulski@pas.rochester.edu>:<br><br></blockquote></div><blockquote type="cite"><div dir="ltr"><span>Joerg:</span><br><span></span><br><blockquote type="cite"><span>„Readable“ is a subjective term.</span><br></blockquote><span></span><br><span>We just discovered that a computer science professor (Hellwig) does not fully understand RISC5 code. Neither do I despite 20 years of VHDL experience. This discovery is a disaster for the NW school of thought. It directly contradicts all NW ideals. How can RISC5 be ever taught to anyone, if the computer science professor has problems with answering some basic questions concerning its architecture? </span><br><span></span><br><span>Lets compare two pieces of code. The 1st is from the latest RISC5. The other is my own translation. It compiles. Let's not dispute whether or not I made a mistake while translating. I am not a Verilog expert. The point is that one style is not readable (subjectively of course), while the other conveys the idea to an engineer or student with only cursory understanding of Verilog.</span><br><span></span><br><span>// Example 1. Code from RISC5.v dated 31.8.2018</span><br><span>assign pcmux = ~rst | stall | intAck | RTI ? </span><br><span> (~rst | stall ? (~rst ? StartAdr : PC) :</span><br><span> (intAck ? 1 : SPC)) : pcmux0;</span><br><span></span><br><span>// Example 2. My translation of the above</span><br><span>// Alternative code. I changed pcmux from wire to reg in order to allow for assignments</span><br><span>always @*</span><br><span> if (~rst | stall | intAck | RTI) </span><br><span> if (~rst | stall) </span><br><span> if (~rst) pcmux = StartAdr; else pcmux = PC; </span><br><span> else </span><br><span> if (intAck) pcmux = 1; else pcmux = SPC; </span><br><span> else pcmux = pcmux0;</span><br><span></span><br><blockquote type="cite"><span>Purely from a compiler construction‘s point of view, the ternary operator ?:; and if-then-else CAN produce exactly the same outout during syntesis but they DON’T have to. </span><br></blockquote><span></span><br><span>If they are equivalent, then according to NW ideals we should code in a human friendly style.</span><br><span></span><br><blockquote type="cite"><span>It heavily depends on the Verilog compiler.</span><br></blockquote><span></span><br><span>Can you substantiate this statement with some examples? </span><br><span></span><br><blockquote type="cite"><span>Generally, for assignments the ternary operator is cleaner as the output of both branches must have the same type.</span><br></blockquote><span></span><br><span>The very same can be achieved under if-then-else. See my example, which is a direct translation. The branches are of the same type as you requested. But the code is cleaner for me, and perhaps to everyone else who was not directly involved in the development.</span><br><span></span><br><span>I suggest that we need two versions of RISC5. One which is coded in a human-friendly way. And perhaps another one optimized for performance but perhaps unreadable to non-experts. </span><br><span></span><br><span>Furthermore, the human-readable code can be perhaps optimized to the same level as human-hostile code. There is no reason why if-then-else (see Example 2) should not be an exact equivalent of the obfuscated code (see Example 1).</span><br><span></span><br><span>The human readable code will consist of more lines. The line count should not be the decisive factor. We need to decide, which ideal is more important: line count or clarity? I vote for the latter.</span><br><span></span><br><span>Thanks,</span><br><span>Wojtek</span><br><span></span><br><span></span><br><span></span><br><span></span><br><span></span><br><span>--</span><br><span>Oberon@lists.inf.ethz.ch mailing list for ETH Oberon and related systems</span><br><span>https://lists.inf.ethz.ch/mailman/listinfo/oberon</span><br></div></blockquote></div></div></body></html>