[Barrelfish-users] A few Qs on NUMA in general

KDA gravaera at gmail.com
Tue Dec 29 01:51:27 MET 2009

Hi, and congratulations on making sense of the mess that is NUMA development
so far, as I have been stumbling into countless holes and pits on my way.
Documentation of any kind is rare and not software-centric.

Please bear with me, as I have not-too-many questions to ask, and they will
not be solely for myself. I intend to compile my learning into articles for
the OSDev.org Wiki, a well known resource for hobbyist OS Developers like

Now, as far as I can tell, The new AMD and Intel processors of the Direct
Connect and Nehalem architecture are going to be coming with a bus
architecture which fully supports NUMA for those architectures. I understand
NUMA fully at a conceptual level, since I have been reading for two weeks
straight, literally non-stop, as many papers as I can get my hands (or
mouse) on. I've browsed you source, and whatnot, and no doubt this is a
really original design.

A question about a NUMA aware kernel being booted: Is there any guarantee
that on boot, the kernel image or bootloader, whichever the firmware loads,
will be loaded into the NUMA memory bank @ that begins at PFN 0x0? As in,
for any architecture, what guarantee is there that the kernel can sanely go
about setting up, for example a bitmap of frames for addresses starting at
say, the end of the kernel image?

In order to do that, the bitmap would need to be multiplied by a page
granularity, such that the first bit, bit 0 would be multiplied by 0x1000,
then given out to the kernel, the second, bit 1, would be multiplied by
0x1000 and give out the PFN 0x1000, and so on. But if a kernel image is
loaded into a NUMA memory bank where the logical mapping is such that the
bank's PFN begins at say 0xF0000000, a kernel that attempts to bootstrap
itself is immediately stunted.

Please, if you have any info on the initialization of memory banks in numa
systems, (even if it's for x86 only), do kindly consider replying.

Another question: It seems like NUMA architectures commonly rely on the ACPI
SLIT/SRAT arrangement to discover node relational distancing. Is ACPI a
uniformly used standard for enumerating nodes and their resources? Would you
say that all numa systems use ACPI? Or at least all the most common
architectures' NUMA capable models do? (x86, PPC, MIPS, ARM).

I have not yer read up on the ACPI specification itself, but simply Ctrl-F'd
it and looked for the information that tells how to find the RSDP. It seems
that they imply in the specification (versions 1 straight through 3) that on
any platform wanting to supply ACPI functionality to the OS, must place the
RSDP in the 1st 1MB of RAM. The specification states that the OS is to
search for the RSDP in the BDA, or in a region of memory just below 1MB.

Is this platform independent? And if so, then it seems it is correct to
state that in order to have NUMA compliant kernel, no matter where it is
ported to, so long as ACPI remains the standard for NUMA enumeration, an OS
should have its executable image loaded above the physical 1MB mark. Am I
correct in saying this?

I thank you abundantly in advance should you see it fit to answer me.

All the absolute best in your own project,
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