[Barrelfish-users] x86 cache patch

[Kornilios Kourtis]

Hi Georgios,

On Wed, Jun 26, 2013 at 09:14:59AM +0000, Georgios Varisteas wrote:
> The reason for this patch stems from a BIOS that does not provide such
> settings and the fact that default configuration is cache-disable.
> Seabios is such, used in simulators.

In that case, I think the best thing would be to: check whether the cache
is disabled and if that's the case enable it, but also print a message to
notify the user.

Also, as I said in my previous e-mail, I'm not so sure about setting
~CR0_NW, which AFAIU disables write-back caching.

cheers,
Kornilios.

> 
> cheers,
> Georgios
> 
> ________________________________________
> From: Kornilios Kourtis [kornilios.kourtis at inf.ethz.ch]
> Sent: Wednesday, June 26, 2013 10:44
> To: Mateusz Olczak
> Cc: barrelfish-users at lists.inf.ethz.ch
> Subject: Re: [Barrelfish-users] x86 cache patch
> 
> Hi Mateusz,
> 
> On Sun, Jun 23, 2013 at 06:00:25PM +0200, Mateusz Olczak wrote:
> > Hi,
> >
> > A while back I asked if caching was enabled for all cores and got the
> > reply it was up to the hardware BIOS to do that for all cores.  Since
> > not all BIOSes do that, I had to make Barrelfish enable caches on all
> > cores for purpose of benchmarking Barrelfish using Simics and g-cache.
> >
> > I've attached the tiny patch.
> > What it does:
> > For x86_32 in arch_init:
> > Moves the enable_caches() out of #ifdef __scc__ and thus enables caches on all cores for x86_32, not only the Intel SCC.
> >
> > For x86_64:
> > Adds the enable_caches() function and calls it in arch_init for x86_64,
> > thus enabling caches on all cores for x86_64.
> >
> 
> Thanks for the patch.
> 
> [snip]
> > +#define CR0_CD  (1 << 30)
> > +#define CR0_NW  (1 << 29)
> > +
> > +static inline void enable_caches(void)
> > +{
> > +    uint64_t cr0;
> > +
> > +    __asm volatile("mov %%cr0, %[cr0]" : [cr0] "=r" (cr0));
> > +    cr0 &= ~CR0_CD;
> > +    cr0 &= ~CR0_NW;
> > +    __asm volatile("mov %[cr0], %%cr0" :: [cr0] "r" (cr0));
> > +}
> 
> As far as I can tell, this globally enables write-back caching which is
> something we might not want on all x86 machines.
> 
> Also, I'm not sure about the whole patch, since if it's something that
> can be configured from BIOS, having Barrelfish silently ignoring the BIOS
> setting might be confusing.
> 
> cheers,
> Kornilios.
> 
> --
> Kornilios Kourtis
> 
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-- 
Kornilios Kourtis