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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hello<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>The ARM port is at a fairly early stage. What is there is being developed on QMEU with an ARMv5TE ISA similar to the IXP/IOP instruction set. At some stage someone will hopefully take it forward to run an I/O card based on one of the these. The benefit of running on something like an IXP will really be felt if someone goes on to target the micro-engines.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>For a contemporary system that did run on an I/O card there’s the Helios paper here: <a href="http://research.microsoft.com/apps/pubs/default.aspx?id=81154">http://research.microsoft.com/apps/pubs/default.aspx?id=81154</a> The benefit of running code on this particular processor was slight. The processor has hardware acceleration for RAID operations and Helios wasn’t exercising this functionality in the paper.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Kind Regards<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Orion<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> barrelfish-bounces@lists.inf.ethz.ch [mailto:barrelfish-bounces@lists.inf.ethz.ch] <b>On Behalf Of </b>Robert Pettersen<br><b>Sent:</b> 07 May 2010 09:31<br><b>To:</b> barrelfish-users@lists.inf.ethz.ch<br><b>Subject:</b> [Barrelfish] [Barrelfish-users] ARM port and programmable network cards<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi there,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I'm a currently working on a research proposal about multi-kernel ideals in network interfaces.<o:p></o:p></p></div><div><p class=MsoNormal>I noticed a paragraph under "Experience and future work" in your paper stating you where working on an ARM port to support programmable network cards.<o:p></o:p></p></div><div><p class=MsoNormal>In that context I was wondering if you had made any progress, or plans on how to integrate I/O devices like a network interface into your implementation of a multi-kernel operating system.<o:p></o:p></p></div><div><p class=MsoNormal>Any information would be greatly appreciated.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>--<o:p></o:p></p></div><div><p class=MsoNormal>Regards,<o:p></o:p></p></div><div><p class=MsoNormal>Robert<o:p></o:p></p></div></div></body></html>