Hi Samuel,<br><br> Yes, you were right. I run hake.sh with the arm_gem5 parameter and then run make without the arm parameter.<br><br> So, running Barrelfish on the old GEM5 revision (d45a02bd5391) with the VExpress_ELT platform, it works. But as I said before, the new GEM5 revision (64db8473f3ab) do not have this platform. So I started to port it to another platform by changing the parameters found in the "barrelfish/kernel/arch/arm_gem5" directory, as the INITRD_BASE on the init.c file according to ramdisk address, or the PIT_BASE on the integrator.c file according to timer (Sp804) address, and so on...<br>
<br> But even with these changes, the Barrelfish did not pass the boot, at least, it shows not message after "info: Entering event queue @ 0. Starting simulation..." in a terminal and "==== m5 slave terminal: Terminal 0 ====" on another. So how do you debug Barrelfish on GEM5??<br>
<br> By the way, I always get the warning "warning: Trying to access an SPSR in invalid mode: 31". Was it not related to the ISA? Such an instruction not supported on ARMv7 that was suported on ARMv5... So, do you have a guess about it?<br>
<br>Ps.: You included only on the GEM5 mailing list, so I put also in the Barrelfish mailing list.<br><br>Best Regards,<br>Rafael Garibotti<br><br><br><div class="gmail_quote">2012/6/19 Samuel Hitz <span dir="ltr"><<a href="mailto:samuel.hitz@gmail.com" target="_blank">samuel.hitz@gmail.com</a>></span><br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Rafael,<div><div><br></div><div>Did you build Barrelfish with 'make arm'? If not please try this and see if it works. It seems like romfs_cpio_archive_size in</div>
<div><div> phys_mmap_remove(&phys_mmap,</div>
<div> <span style="white-space:pre-wrap"> </span> INITRD_BASE,</div><div> <span style="white-space:pre-wrap"> </span> INITRD_BASE + romfs_cpio_archive_size);</div><div>
<br></div><div>in init.c:arch_init is 0 which happens if you don't build Barrelfish with 'make arm'. </div><div><br></div>Cheers,</div><div><br></div><div>Samuel</div><div><br></div><div>(adding barrelfish-mailing list. You should ask questions there so that everyone can possibly answer you or gain something from the solutions posted)</div>
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<div><br><div class="gmail_quote">On Tue, Jun 19, 2012 at 4:47 PM, Rafael Garibotti <span dir="ltr"><<a href="mailto:rafaelgaribotti@gmail.com" target="_blank">rafaelgaribotti@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Samuel,<br><br> I tried using the GEM5 simulator with the Barrelfish, but I always got the same error:<br><br>-------------------------------------------------------------------<br>Barrelfish CPU driver starting on ARMv7 Board id 0x000008e0<br>
The address of paging_map_kernel_section is 0xc0022e00<br>kernel PANIC! kernel assertion "limit > start" failed at ../kernel/arch/arm/phys_mmap.c:130<br>-------------------------------------------------------------------<br>
<br> Do you know how I can fix this problem?<br><br> I tried using the latest GEM5 revision (64db8473f3ab), but I saw that the platform used (VExpress_ELT) is no longer available, so before starting to migrate to another platform (i.e. RealView_PBX), I took the version indicated in the README file (d45a02bd5391) and even making the changes indicated, the error shown above remains.<br>
<br> So, I tested the RealView_PBX platform and I needed to change the memory size to not have two devices with the same address. After that, the Barrelfish starting the simulation as shown below, but unfortunately it doesn't boot... :( ... That means I need to change the bootloader... So do you have any tips on how to proceed before I start looking for it?<br>
<br>-------------------------------------------------------------------<br>..... STARTING SIMULATION<br>info: Entering event queue @ 0. Starting simulation...<br>-------------------------------------------------------------------<br>
<br> Thank you!!<br><br>Best Regards,<br>Rafael Garibotti<br>
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