diff --git a/kernel/arch/arm_gem5/init.c b/kernel/arch/arm_gem5/init.c index 9682571..78ec5a4 100644 --- a/kernel/arch/arm_gem5/init.c +++ b/kernel/arch/arm_gem5/init.c @@ -182,7 +182,7 @@ struct atag { static int timeslice = 5; //interval in ms in which the scheduler gets called static int serial_console_port = 0; -static int serial_debug_port = 1; +static int serial_debug_port = 0; static struct cmdarg cmdargs[] = { { "consolePort", ArgType_Int, { .integer = &serial_console_port}}, diff --git a/kernel/arch/arm_gem5/integrator.c b/kernel/arch/arm_gem5/integrator.c index 6aef467..4ffb538 100644 --- a/kernel/arch/arm_gem5/integrator.c +++ b/kernel/arch/arm_gem5/integrator.c @@ -48,9 +48,9 @@ static uint32_t tsc_hz = 1000000000; // Interrupt controller // -#define PIC_BASE 0xE0200000 +#define PIC_BASE 0x2C000000 #define DIST_OFFSET 0x1000 -#define CPU_OFFSET 0x100 +#define CPU_OFFSET 0x2000 static pl130_gic_t pic; static pl130_gic_ICDICTR_t pic_config; @@ -327,12 +327,12 @@ void pic_ack_irq(uint32_t irq) // Kernel timer and tsc // -#define PIT_BASE 0xE0000000 -#define PIT0_OFFSET 0x11000 -#define PIT_DIFF 0x1000 +#define PIT_BASE 0x1C100000 +#define PIT0_OFFSET 0x10000 +#define PIT_DIFF 0x10000 -#define PIT0_IRQ 36 -#define PIT1_IRQ 37 +#define PIT0_IRQ 34 +#define PIT1_IRQ 35 #define PIT0_ID 0 #define PIT1_ID 1 @@ -472,8 +472,8 @@ void pit_mask_irq(bool masked, uint8_t pit_id) // TSC uses cpu private timer // -#define TSC_BASE 0xE0200000 -#define TSC_OFFSET 0x600 +#define TSC_BASE 0x2C000000 +#define TSC_OFFSET 0x80000 static cortex_a9_pit_t tsc; @@ -537,7 +537,7 @@ int scu_get_core_count(void) // Sys Flag Register // -#define SYSFLAGSET_BASE 0xFF000030 +#define SYSFLAGSET_BASE 0x1C010030 lpaddr_t sysflagset_base = SYSFLAGSET_BASE; void write_sysflags_reg(uint32_t regval) @@ -550,10 +550,10 @@ void write_sysflags_reg(uint32_t regval) // #define CONSOLE_PORT 0 -#define DEBUG_PORT 1 +#define DEBUG_PORT 0 -#define UART0_VBASE 0xE0009000 -#define UART0_SECTION_OFFSET 0x9000 +#define UART0_VBASE 0x1c090000 +#define UART0_SECTION_OFFSET 0x90000 #define UART_DEVICE_BYTES 0x4c #define UART_MAPPING_DIFF 0x1000 diff --git a/tools/arm_gem5/CacheConfig.py b/tools/arm_gem5/CacheConfig.py index 009cb1b..bc724f6 100644 --- a/tools/arm_gem5/CacheConfig.py +++ b/tools/arm_gem5/CacheConfig.py @@ -43,7 +43,7 @@ def config_cache(options, system): system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, block_size=options.cacheline_size) - system.tol2bus = Bus() + system.tol2bus = CoherentBus() system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave diff --git a/tools/arm_gem5/Caches.py b/tools/arm_gem5/Caches.py index 0be8001..0feec3c 100644 --- a/tools/arm_gem5/Caches.py +++ b/tools/arm_gem5/Caches.py @@ -31,7 +31,8 @@ from m5.objects import * class L1Cache(BaseCache): assoc = 2 block_size = 64 - latency = '1ns' + hit_latency = '1' + response_latency = '1' mshrs = 10 tgts_per_mshr = 20 is_top_level = True @@ -39,14 +40,16 @@ class L1Cache(BaseCache): class L2Cache(BaseCache): assoc = 8 block_size = 64 - latency = '10ns' + hit_latency = '10' + response_latency = '10' mshrs = 20 tgts_per_mshr = 12 class PageTableWalkerCache(BaseCache): assoc = 2 block_size = 64 - latency = '1ns' + hit_latency = '1' + response_latency = '1' mshrs = 10 size = '1kB' tgts_per_mshr = 12 @@ -55,7 +58,8 @@ class PageTableWalkerCache(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - latency = '10ns' + hit_latency = '10' + response_latency = '10' mshrs = 20 size = '1kB' tgts_per_mshr = 12 diff --git a/tools/arm_gem5/O3_ARM_v7a.py b/tools/arm_gem5/O3_ARM_v7a.py index 68fb0c5..6eb639b 100644 --- a/tools/arm_gem5/O3_ARM_v7a.py +++ b/tools/arm_gem5/O3_ARM_v7a.py @@ -147,7 +147,7 @@ class O3_ARM_v7a_3(DerivO3CPU): # Instruction Cache # All latencys assume a 1GHz clock rate, with a faster clock they would be faster class O3_ARM_v7a_ICache(BaseCache): - latency = '1ns' + response_latency = '1' block_size = 64 mshrs = 2 tgts_per_mshr = 8 @@ -158,7 +158,7 @@ class O3_ARM_v7a_ICache(BaseCache): # Data Cache # All latencys assume a 1GHz clock rate, with a faster clock they would be faster class O3_ARM_v7a_DCache(BaseCache): - latency = '2ns' + response_latency = '2' block_size = 64 mshrs = 6 tgts_per_mshr = 8 @@ -170,7 +170,7 @@ class O3_ARM_v7a_DCache(BaseCache): # TLB Cache # Use a cache as a L2 TLB class O3_ARM_v7aWalkCache(BaseCache): - latency = '4ns' + response_latency = '4' block_size = 64 mshrs = 6 tgts_per_mshr = 8 @@ -183,7 +183,7 @@ class O3_ARM_v7aWalkCache(BaseCache): # L2 Cache # All latencys assume a 1GHz clock rate, with a faster clock they would be faster class O3_ARM_v7aL2(BaseCache): - latency = '12ns' + response_latency = '12' block_size = 64 mshrs = 16 tgts_per_mshr = 8 @@ -192,5 +192,5 @@ class O3_ARM_v7aL2(BaseCache): write_buffers = 8 prefetch_on_access = 'true' # Simple stride prefetcher - prefetcher = StridePrefetcher(degree=8, latency='1.0ns') + prefetcher = StridePrefetcher(degree=8, latency=1) diff --git a/tools/arm_gem5/README b/tools/arm_gem5/README index 70c0e00..f61a27e 100644 --- a/tools/arm_gem5/README +++ b/tools/arm_gem5/README @@ -4,16 +4,13 @@ ARM on Gem5 usage and installation instructions: 2. If you are a member of ETH or Microsoft Research with access to the Barrelfish development tools continue with point 6 otherwise do steps 3 to 5 -3. Get the gem5 simulator with 'hg clone hg clone http://repo.gem5.org/gem5 -r d45a02bd5391 gem5' (note you have to use this release to get a working environment out of the box) +3. Get the gem5 simulator with 'hg clone http://repo.gem5.org/gem5 -r 0fea324c832c gem5' (this is the current mercurial tip of Gem5 but future versions may also work) -4. Change to your gem5 directory and apply 'gem5_patches.patch', located in '/path/to/barrelfish/tools/arm_gem5' to the gem5 source code +4. Build gem5 with 'scons build/ARM/gem5.fast' and add the binary to the PATH -5. Build gem5 with 'scons build/ARM/gem5.fast' and add the binary to the PATH - NOTE: I had to use an older version of gcc, gcc 4.4 - 4.6 worked for me. If you have troubles install gcc 4.4 and compile with 'CXX=g++-4.4 scons build/ARM/gem5.fast' +5. In your Barrelfish build directory run 'make arm_gem5' to run the simulation -6. In your Barrelfish build directory run 'make arm_gem5' to run the simulation - -7. To get the output of Barrelfish you can use 'telnet localhost 3456' +6. To get the output of Barrelfish you can use 'telnet localhost 3456' NOTE 1: You can print the supported options of the gem5 script with 'gem5.fast ../tools/gem5/gem5script.py -h' NOTE 2: If you use --cpu-type=arm_detailed (use make arm_gem5_detailed), the simulation takes a long time (depending on your machine up to an hour just to boot Barrelfish) \ No newline at end of file diff --git a/tools/arm_gem5/gem5_patches.patch b/tools/arm_gem5/gem5_patches.patch deleted file mode 100644 index 7cfbe25..0000000 --- a/tools/arm_gem5/gem5_patches.patch +++ /dev/null @@ -1,93 +0,0 @@ -diff -rupN gem5-d45a02bd5391/src/arch/arm/linux/system.cc gem5/src/arch/arm/linux/system.cc ---- gem5-d45a02bd5391/src/arch/arm/linux/system.cc 2012-05-19 13:32:25.000000000 +0200 -+++ gem5/src/arch/arm/linux/system.cc 2012-06-22 12:18:15.243128313 +0200 -@@ -59,29 +59,11 @@ LinuxArmSystem::LinuxArmSystem(Params *p - : ArmSystem(p) - { - #ifndef NDEBUG -- kernelPanicEvent = addKernelFuncEvent("panic"); -- if (!kernelPanicEvent) -- panic("could not find kernel symbol \'panic\'"); -+ // kernelPanicEvent = addKernelFuncEvent("panic"); -+ // if (!kernelPanicEvent) -+ // panic("could not find kernel symbol \'panic\'"); - #endif - -- // With ARM udelay() is #defined to __udelay -- Addr addr = 0; -- if (kernelSymtab->findAddress("__udelay", addr)) { -- uDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__udelay", -- fixFuncEventAddr(addr), 1000, 0); -- } else { -- panic("couldn't find kernel symbol \'udelay\'"); -- } -- -- // constant arguments to udelay() have some precomputation done ahead of -- // time. Constant comes from code. -- if (kernelSymtab->findAddress("__const_udelay", addr)) { -- constUDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__const_udelay", -- fixFuncEventAddr(addr), 1000, 107374); -- } else { -- panic("couldn't find kernel symbol \'udelay\'"); -- } -- - secDataPtrAddr = 0; - secDataAddr = 0; - penReleaseAddr = 0; -diff -rupN gem5-d45a02bd5391/src/dev/arm/gic.cc gem5/src/dev/arm/gic.cc ---- gem5-d45a02bd5391/src/dev/arm/gic.cc 2012-05-19 13:32:25.000000000 +0200 -+++ gem5/src/dev/arm/gic.cc 2012-06-22 12:18:07.419795269 +0200 -@@ -193,12 +193,12 @@ Gic::readDistributor(PacketPtr pkt) - pkt->set(int_p[int_num]); - break; - case 2: -- assert((int_num + 1) < (SGI_MAX + PPI_MAX)); -+ assert((int_num + 1) < (INT_LINES_MAX)); - pkt->set(int_p[int_num] | - int_p[int_num+1] << 8); - break; - case 4: -- assert((int_num + 3) < (SGI_MAX + PPI_MAX)); -+ assert((int_num + 3) < (INT_LINES_MAX)); - pkt->set(int_p[int_num] | - int_p[int_num+1] << 8 | - int_p[int_num+2] << 16 | -diff -rupN gem5-d45a02bd5391/src/dev/arm/RealView.py gem5/src/dev/arm/RealView.py ---- gem5-d45a02bd5391/src/dev/arm/RealView.py 2012-05-19 13:32:25.000000000 +0200 -+++ gem5/src/dev/arm/RealView.py 2012-06-22 12:18:10.433128490 +0200 -@@ -320,7 +320,8 @@ class RealViewEB(RealView): - class VExpress_ELT(RealView): - max_mem_size = '2GB' - pci_cfg_base = 0xD0000000 -- elba_uart = Pl011(pio_addr=0xE0009000, int_num=42) -+ uart0 = Pl011(pio_addr=0xE0009000, int_num=42) -+ uart1 = Pl011(pio_addr=0xE000A000, int_num=43) - uart = Pl011(pio_addr=0xFF009000, int_num=121) - realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000) - gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100) -@@ -350,7 +351,6 @@ class VExpress_ELT(RealView): - - l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff) - dmac_fake = AmbaFake(pio_addr=0xE0020000) -- uart1_fake = AmbaFake(pio_addr=0xE000A000) - uart2_fake = AmbaFake(pio_addr=0xE000B000) - uart3_fake = AmbaFake(pio_addr=0xE000C000) - smc_fake = AmbaFake(pio_addr=0xEC000000) -@@ -380,7 +380,8 @@ class VExpress_ELT(RealView): - # earlier, since the bus object itself is typically defined at the - # System level. - def attachIO(self, bus): -- self.elba_uart.pio = bus.master -+ self.uart0.pio = bus.master -+ self.uart1.pio = bus.master - self.uart.pio = bus.master - self.realview_io.pio = bus.master - self.v2m_timer0.pio = bus.master -@@ -407,7 +408,6 @@ class VExpress_ELT(RealView): - - self.l2x0_fake.pio = bus.master - self.dmac_fake.pio = bus.master -- self.uart1_fake.pio = bus.master - self.uart2_fake.pio = bus.master - self.uart3_fake.pio = bus.master - self.smc_fake.pio = bus.master diff --git a/tools/arm_gem5/gem5script.py b/tools/arm_gem5/gem5script.py index 7ad9093..a67390f 100644 --- a/tools/arm_gem5/gem5script.py +++ b/tools/arm_gem5/gem5script.py @@ -25,7 +25,7 @@ from Caches import * bfsrcdir='%s/../..' % os.path.dirname(inspect.getfile(inspect.currentframe())) print "Barrelfish source-directory is assume to be %s" % bfsrcdir -class MemBus(Bus): +class MemBus(CoherentBus): badaddr_responder = BadAddr() default = Self.badaddr_responder.pio @@ -101,24 +101,22 @@ parser.add_option("--loglevel", type="int", default=4) (CPUClass, mem_mode, FutureClass) = setCPUClass(options) -system = LinuxArmSystem() +system = ArmSystem() #kernel to boot system.kernel = options.kernel #memory system -system.iobus = Bus(bus_id=0) -#system.iobus = NoncoherentBus() -system.membus = MemBus(bus_id=1) -#system.membus = MemBus() +system.iobus = NoncoherentBus() +system.membus = MemBus() system.membus.badaddr_responder.warn_access = "warn" -system.bridge = Bridge(delay='50ns', nack_delay='4ns') +system.bridge = Bridge(delay='50ns') system.bridge.master = system.iobus.slave system.bridge.slave = system.membus.master -system.physmem = SimpleMemory(range = AddrRange('512MB'),conf_table_reported = True) +system.physmem = SimpleMemory(range = AddrRange('256MB'),conf_table_reported = True) system.mem_mode = mem_mode #load ramdisk at specific location (256MB = @0x10000000) @@ -130,8 +128,7 @@ CPUClass.clock = "1GHz" system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] #machine type -system.machine_type = "VExpress_ELT" -system.realview = VExpress_ELT() +system.realview = VExpress_EMM() #setup bootloader system.realview.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), size = '64MB'), zero = True) @@ -163,7 +160,7 @@ if options.caches or options.l2cache: system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave else: - system.iobridge = Bridge(delay='50ns', nack_delay='4ns', + system.iobridge = Bridge(delay='50ns', ranges = [system.physmem.range]) system.iobridge.slave = system.iobus.master system.iobridge.master = system.membus.slave