[Oberon] Parallel processing

Douglas G. Danforth Danforth at GreenwoodFarm.com
Tue Jan 30 22:28:02 MET 2007

Thank you for the fast response and reference. I am in the process of 
reading it. One thought occurs to me engendered by that report and that 
is the following.

I worked for four years at NASA Ames within their Research Institute for 
Advance Computer Science (RIACS) on a project developed at Stanford by 
Pentti Kanerva.  Kanerva's Sparse Distributed Memory (SDM) is a 
massively parallel architecture that computes in one cycle. 

Random Access Memory (RAM) is fast because it is massively parallel.  A 
32 bit address is broadcast simultaneously to all locations in memory 
and only one of those addresses responds by placing its contents on the 
output bus (read operation) or by modifying its contents from the input 
bus (write operation).

SDM is very similar except it uses addresses of thousands of bits.  One 
can not represent all possible memory addresses for thousands of bits so 
a sparse sampling of those locations is chosen.  When an address is 
presented to the memory more than a single location responds (nearest k 
locations) and they pool their contents to produce output or modify 
(increment) their contents for input.

What does this have to do with computing?  It is the next level for it 
is a pattern matching and completion machine.  Presented with an image 
of a fuzzy "O" it is possible to clean it up and retrieve a very good 
representation of an O (actual experiment performed).  It can do face 
recognition, speech recognition, weather prediction, handwriting 
recognition, and other pattern matching tasks.

SDM is a beast of a different kind and still many years in the future 
for hardware to catch up with the concept.  It doesn't suffer, however, 
from issues of threads and programming.  It is a learning machine.

I just wanted to get that idea on the table.

Now back to our regularly scheduled program!

-Doug Danforth

Brantley Coile wrote:
> http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-1.html
>> "In an InformationWeek article entitled 'Where's the Software to Catch 
>> Up to Multicore Computing?' the Chief Architect at IBM gives some fairly 
>> compelling reasons why your favorite software will soon be rendered 
>> deadly slow because of new hardware architectures. Software, she says, 
>> just doesn't understand how to do work in parallel to take advantage of 
>> 16, 64, 128 cores on new processors. Intel just stated in an SD Times 
>> article that 100% of its server processors will be multicore by end of 
>> 2007. We will never, ever return to single processor computers. 
>> Architect Catherine Crawford goes on to discuss some of the ways 
>> developers can harness the 'tiny supercomputers' we'll all have soon, 
>> and some of the applications we can apply this brute force to."
>> --
>> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
>> https://lists.inf.ethz.ch/mailman/listinfo/oberon
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

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