[Oberon] Ceres documents scanned
paulreed at paddedcell.com
Fri Dec 7 16:25:16 CET 2012
For those who are interested in the history of Oberon and the Ceres
Workstation on which it was first used:
Two documents which were not previously available digitally have recently
been scanned and added to ETH's digitised collection at
Author: Beat Heeb
Title: Design of the Processor-Board for the Ceres-2 Workstation
Technical Reports 93, ETH Zürich, Institut fuer Informatik, 11 1988.
Ceres is a single user workstation based on the NS32032 microprocessor.
The NS32532, a new, more powerful, but fully software compatible member of
the NS32000 family made it possible to enhance the performance of the
machine without much effort. Because of the modular structure of the
Ceres, only the processor board had to be changed, while the rest of the
hardware and all software (except device handlers) remained unchanged.
This paper describes the differences between the new processor board and
the old one and presents the result of some performance measurements.
title :Development and Analysis of a Workstation Computer
author :Johann Jakob Eberle
institution : ETH Zürich
address :Institut fuer Informatik
type :PhD Thesis
The workstation Ceres is a stand-alone computer for a single user. The
design is an example of a simple system architecture reflected by a
careful implementation with minimal costs. Ceres is based on the 32-bit
microprocessor NS32032, which is oriented to the use of high-level and
modular languages. A key feature is the high-resolution bitmapped graphics
display which is attractive for applications such as program development
or document processing. The arbitrated memory bus and the modular system
organization are open to future hardware extensions.
This thesis documents the hardware development of the workstation Ceres.
The design objectives of the raster graphics interface and of the bus
structure are discussed in detail. Finally, processor-memory
communication of two prototype versions is analysed, which differ only in
the width of their data paths to memory.
The raster graphics interface of Ceres contains an integral frame buffer
memory, which is directly addressable by the CPU. The frame buffer is
based on video RAM technology which ideally meets the high video bandwidth
requirements of the 1024 x 800 non-interlaced display. An inexpensive and
flexible solution is retained by dispensing with dedicated hardware
support for image manipulation.
The backbone of the Ceres computer is the memory bus, which is shared by
multiple master devices. The bus is controlled by a centralized arbiter.
Short response times are ensured in that the shared memory is re-allocated
for every memory cycle according to fixed priorities. A default
assignment strategy prevents the processor from being significantly slowed
by arbitration delays.
The analysis of processor-memory communication is motivated by the
observed small benefit in performance gained by replacing the NS32016 CPU
with the NS32032 CPU and thus doubling the memory bus bandwidth.
[Measurements] show that the bus capacity of the NS32032-based Ceres is
only used to a small degree. Therefore, the additional costs can
hardly be justified. This contrasts with the frequently heard claims of
the superiority of 32-bit computers.
More information about the Oberon