[Oberon] Project Oberon: New Edition

[Simon Forman]

This is awesome. A great Christmas present.

I don't have an FPGA dev board, so I started a crude attempt to host a
virtual Oberon using Python. I'm working on a simulator for the RISC
chip and a transliteration of the Oberon compiler into Python to
generate binary code to bootstrap.

https://github.com/PhoenixBureau/PythonOberon

I hadn't noticed the verilog sources, so I'm using a Python hardware
description language called MyHDL to model the RISC chip.  Now that I
know about them-- Thank you! --I may switch to using them.

I also started to try to make an Oberon-to-Python converter using
something called a PEG parser, but I got impatient and switched to
simply "rewriting" the compiler code in Python.  (I put "rewriting" in
quotes because the two languages are so similar syntactically that
much of the conversion is doable by search and replace and a few
regular expressions.  The tricky bit is that Python and Oberon handle
argument passing very differently.)

If I can get a fully-Python-hosted virtual Oberon system working I'll
be sure to mention it on this list. Cheers!
~Simon


On 12/20/13, Chris Burrows <chris at cfbsoftware.com> wrote:
> Yes - it is still a 'work in progress' but the Language Report, CPU
> description and Verilog sources are currently on the other pages of Wirth's
> website:
>
> http://www.inf.ethz.ch/personal/wirth/
>
> There is also an updated version of Compiler Construction book.
>
> LONGINT is just an alias for INTEGER and the complete CASE statement is on
> its way,
>
> A version of Astrobe that supports the FPGA compiler is well underway ...
>
> Regards,
> Chris
>
> Chris Burrows
> CFB Software
> http://www.astrobe.com
>
>
> From: Alexey Veselovsky [mailto:alexey.veselovsky at gmail.com]
> Sent: Friday, 20 December 2013 10:30 PM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] Project Oberon: New Edition
>
> I think that Project Oberon rev 2013 not complete yet.
>
> For example Annex A1 and Annex A2 (language report and CPU
> description) still not published. Also there are no Verilog sources.
>
>
>
> RISC emulator module still written in Oberon rev 1990 (old CASE semantic
> detected).
>
> Whole system and compiler are written in strange language - it is not
> Oberon
> 1990 nor Oberon rev 2013 (LONGINT and other types that has disappeared in
> Oberon 07/13, but new semantic for CASE that not described even in Oberon
> rev 2013 report).
>
> Also there are some typos, for example in 17.2.4: "From a 15 MHz clock rate
> results a refresh rate of 53.5 frames/s" should be replaced to "From a 25
> MHz clock rate results a refresh rate of 53.5 frames/s".
>
> Also I can't found description for clk25 in XGA Verilog module (what
> difference from clk?).
>
> We discuss Project Oberon 2013 here (in Russian)
> : http://oberspace.dyndns.org/index.php/topic,597.0.html
>
> Thanks, Alexey.
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>
>
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>


-- 
http://twitter.com/SimonForman
My blog: http://firequery.blogspot.com/
Also my blog: http://calroc.blogspot.com/



"The history of mankind for the last four centuries is rather like that of
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