[Oberon] Project Oberon: New Edition

[Alexey Veselovsky]

Have found answer here
http://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC.pdf:

Register instructions contain two modifier bits u and v. The instruction
> MOV with u set to 1 shifts the
> immediate value im by 16 bits to the left. Instructions ADD and SUB with
> the modifier bit u set to 1 add
> (subtract) the carry bit C, and the MUL instruction with u set to 1
> considers the operands as unsigned
> numbers, yielding a 64-bit unsigned product.


Sorry for spam.



On Sun, Dec 22, 2013 at 7:10 PM, Alexey Veselovsky <
alexey.veselovsky at gmail.com> wrote:

> And another question: what u-flag does for register instructions? (there
> is no information about it in latest Compiler Conctruction and Project
> Oberon book)
>
> For example:
>
>
>   PROCEDURE Put1a(op, a, b, im: LONGINT);
>   BEGIN (*same as Pu1, but with range test  -10000H <= im < 10000H*)
>
>     IF (im >= -10000H) & (im <= 0FFFFH) THEN Put1(op, a, b, im)
>     ELSE Put1(Mov+U, RH, 0, im DIV 10000H);
>
>       IF im MOD 10000H # 0 THEN Put1(Ior, RH, RH, im MOD 10000H) END ;
>       Put0(op, a, b, RH)
>     END
>
>   END Put1a;
>
> Put1(Mov+U, RH, 0, im DIV 10000H); -- why we set U-flag here?
>
> Is U means something like shift?
>
> Thanks, Alexey
>
>
>
> On Sun, Dec 22, 2013 at 5:53 PM, Alexey Veselovsky <
> alexey.veselovsky at gmail.com> wrote:
>
>> Hi.
>>
>> Anybody knows what the difference between STW/LDW instructions from
>> Compiler Construction (last revision) and STR/LDR from Project Oberon 2013?
>>
>> Thanks, Alexey.
>>
>
>
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