[Oberon] Oberon Hardware Description Language

[Simon Forman]

On 12/26/13, Jan Verhoeven <jan at verhoeven272.nl> wrote:
> On Thursday 26 December 2013 18:05:27 Srinivas Nayak wrote:
>
>> What would it take Oberon to be able to describe hardware and replace
>> Verilog? Just a wish. If Oberon can be modified such that it can
>> describe software and hardware both, wouldn't it be nice to have one
>> simple, elegant language for all, OS, Compiler, Hardware, Applications
>> all in one language?
>
> I see it like this:
>
> Verilog is a TIG welder.
> Oberon is a urethane glue
>
> Both can make fabulous joints. But it's hard to imagine that both sprout
> from one device.
>
> Unless, of course, you would like to end up with a compiler as complex
> as gcc.
> Verilog deals with matter; it defines silicon, and it is a kind of fuzzy
> logic. Order of execution is not fixed.
> Oberon deals with electrical charges, ordered in one specific sequence
> of 0's and 1's. Order of execution is of the utmost importance.
>
> Verilog uses a syntax that, from afar, resembles Modula-2, but that's as
> far as things go.
>
> --
> Met vriendelijke groeten,
>
> Jan Verhoeven
> http://www.verhoeven272.nl
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>

An (incomplete) attempt to model the RISC in a python HDL:

https://github.com/PhoenixBureau/PythonOberon/blob/master/OPY13/risc.py

The logic is odd from the POV of a programmer, but it makes sense as
digital {concurrent) circuitry.  Neat, eh?

Happy holidays!
Simon