[Oberon] Active Cells / Oberon
greim at schleibinger.com
Mon Dec 30 15:25:04 CET 2013
i tried to understand th "Active Cell" design as far as possible from
the both papers. I must say at the 2nd half if the slides i was a little
- i think its very demanding to make a "free dataflow" design instead of
a mesh like (for example the GA144 from GreenArray or the XMOS chips **)
or a ring architecture (like the Parallax Propeller I or II **)
- the Message passing multiprocessing in the Erlang way is also a good
design decision, i think.
On the last pages, it was a little bit confusing.
- its not really clear for me what the difference between ActiveCells I
and II is.
- you focus onto the Xilinx Zync. Its like the Altera Aria an ARM +
FPGA. Does this mean the the main focus is shifted back to a classical
processor architecture, or is this just for enhanced I/O?
- i can understand c# instead / parallel to Oberon because M$ is
sponsoring the project, ok, ;-)
- on slide 127 there are, i guess, compile times for the logic synthesis
of 20 min. Did i understand this right? Thats the bottleneck, as you
know. OK that may be reduced with faster computers, but the complexity
of the FPGA is increasing at least in the speed of Moors law, so 20 min
will be also 20 min in the future. I habe no real idea how to solve this
problem, but i believe, we must design a HDL which is very primitive and
strongly related to the cell design of the FPGAs.
Some FORTH for FPGA. FORTH in the sense of something very related to the
hardware, not in the sense of a stack machine.
It would be nice if you will publish the latest results of the Active
Cell design project from time to time here in the mailing list.
** P.S. The processors or the RISC cores of the processor cores
mentioned above could be good examples for the Oberon RISC machine. Or
whats about an abstract machine, written in FORTH?
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