[Oberon] FPGA Oberon on projectoberon: Verilog instead of VHDL

[Chris Burrows]

> -----Original Message-----
> From: Jan Verhoeven [mailto:jan at verhoeven272.nl]
> Sent: Wednesday, 26 February 2014 1:30 AM
> To: fp at vonck.nl; ETH Oberon and related systems
> Subject: Re: [Oberon] FPGA Oberon on projectoberon: Verilog instead of
VHDL
> 
> Frans-Pieter Vonck wrote
> > On Verilog:
> > ---------------
> > "The designers of Verilog wanted a language with syntax similar to the
> > C programming language [..]"
> >
> > Anyone has an idea why Wirth choose Verilog instead of VHDL?
> 
> I happened to meet Dennis Ritchey lately and he mentioned about this:
> "Wirth is getting older and wiser..."
> 

Who's Dennis Ritchey? Presumably you didn't mean Dennis Ritchie as he died a
couple of years ago. Or maybe you were joking and forgot the smiley?