[Oberon] FPGA Oberon: how is it done...

[Jörg]

FP

>Still; compare the readabilty of the code of the rs232 driver written in
>verilog with one written in vhdl
>
>verilog
>http://www.inf.ethz.ch/personal/wirth/ProjectOberon/SourcesVerilog/RS232R.v

Please find the description of the RS232 algorithm here (chapter 17.2.5,
page 20)
http://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.Computer.pdf

Perhaps the Verilog gets more obvious if you read the description (what
"midtick" does, what "run" is meant for...)

Jörg

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