[Oberon] FPGA Oberon some news and a reply to F.P.

[Jörg Straube]

Jan

* JUMP is a conditional branch instruction where the condition is "always". The mnemonic is simply "B" with an offset.
* CALL is a branch "always" where additionally the PC is stored in register 15 as link back. The mnemonic is called "BL" (branch and link) with an offset.
* RETURN is a branch "always" where the destination address is taken from (link) register 15. the mnemonic is "B R15".

BTW: "MOV 1, 2" is syntactically not used. We would write "MOV R1 R0 2". ("would" as nobody every writes code with these RISC instructions, remember only the Oberon compiler generates these instructions)    Due to the regularity of the RISC instruction set, all register instructions use TWO registers. As MOV only needs ONE, the second (unused) register is filled with 0 and hence called "R0".

br, Jörg

> Am 05.03.2014 um 19:58 schrieb Jan Verhoeven <jan at verhoeven272.nl>:
> 
> No no, the 6502 was a second generation CISC CPU. The first RISC was 
> probably the MIPS and perhaps the first ARM cpu used in the Archimedes. 
> The MicroChip PIC was the first RISC processor to enter the market on a 
> large scale in the early 90's. And of course the Atmel AVR. And more later.
> 
> What I am disappointed about is the fact that Wirth fell back to 
> undecipherable mnemonics for his newly defined CPU.
> 
> The 6502 and 6800 were known for their BRA's. Intel 8080 was not much 
> better with their DAD and LXI. The guys at Zilog used more letters and 
> better acronyms: LD and RET. Zilog source code is one of the easiest to 
> read back. Even after 30 years.
> 
> The 8086 is good readable too, as long as you reverse the operands... 
> Intel moves backwards.
> PIC uses CLR, SUBWF, INCF etc which has a very steep learning curve. The 
> AVR is a bit like the 6xxx series but not too hard to learn.
> 
> And then came RISC5 which gave us mnemonics that look like the 
> predecessor of the 6800...
> 
> And, worst of all, WHY would you want to fall back to mnemonics? Why do 
> you need to use
> 
> MOV 1, 2 (which looks stupid)
> 
> when you can also use
> 
> Load R1, 2 (which looks logical)
> 
> or, even better:
> 
> R1 := 2 (which leaves no doubt at all)
> 
> Mnemonics were inevitable in times when RAM was priced per bit and cpu 
> clocks were measured in kHz.
> 
> Until now, the future started in Zurich. Mnemonics are a thing from the 
> past. We don't need them anymore. We have fast processors with more RAM 
> than my first HDD.
> 
> I didn't see any jump, call and return instructions in the specification 
> either.
> 
> 
> --
>     Groetjes
> 
> Jan Verhoeven
> 
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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