[Oberon] Spartan 6 Kickstarter project
Ulrich Hoffmann
uho at xlerb.de
Mon Jun 23 18:45:16 CEST 2014
Hello Jörg, Paul,
according to Jack Gasset, developer of the Papilio DUO, the 2MB RAM on the Deluxe board
is organized by 8 :-(
He wrote:
> Unfortunately there are not enough free pins with the Spartan6 tqfp package used on the Papilio DUO to pull that off. The 2MB SRAM is an 8 bit part.
Thanks Paul for pointing this out and explaining the simplicity philosophy.
Regards,
Ulrich
Am 23.06.2014 um 15:43 schrieb Jörg:
> Hi Paul
>
> Today's RISC5Top Verilog source splits the 20 bits address bus to
> two SRAM chips with 18 bits address and 16 bit output.
> +------+
> +-! 256K !-- 16 bit
> ! +------+
> adr (20bit) --- SRadr (18bit) --+
> ! +------+
> +-! 256K !-- 16 bit
> +------+
>
> As the Papilio DUO page only points to ONE SRAM datasheet (IS61WV5128)
> but offers TWO versions of the board (512K and 2M) I could imagine that
> the 2M version has 4 of those chips in parallel.
>
> If this is the case, today's "RISC5Top" Verilog could be re-written to
> +------+
> +-! 512K !-- 8 bit
> ! +------+
> ! +------+
> +-! 512K !-- 8 bit
> adr (20 bit) --- SRadr (18bit) -! +------+
> ! +------+
> +-! 512K !-- 8 bit
> ! +------+
> ! +------+
> +-! 512K !-- 8 bit
> +------+
>
> The upper half of those SRAM chips would not be used...
>
> br
> Jörg
>
>
> -----Original Message-----
> From: Paul Reed [mailto:paulreed at paddedcell.com]
> Sent: Montag, 23. Juni 2014 13:45
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] Spartan 6 Kickstarter project
>
> Hi Ulrich, (bcc others)
>
>> the Papilo DUO kickstarter project [1] (4 days to go) has 2MB SRAM (not
>> SDRAM) on board of its PAPILIO DUO DELUXE.
>>
>> With the Classic Computing Shield you also get VGA output, 2 x PS/2 and
> a micro SD socket.
>>
>> Looks to me, that's what you need for RISC-Project-Oberon, right?
>
>>
> https://www.kickstarter.com/projects/13588168/papilio-duo-drag-and-drop-fpga
> -circuit-lab-for-mak
>
> Looks perfect, but the devil is in the detail, as always. I think their
> SRAM is x8, so even though it's a good speed (10nS), the board seems to be
> designed for retro 8-bit processors not 32-bit RISC. The Digilent
> Spartan-3 board has two x16 10nS SRAMs set up in parallel, which is why
> it's so neat.
>
> However, maybe things are changing - it's refreshing that the Papilio
> project description says: "SRAM - Easy to use SRAM is a must. We've used
> SDRAM in the past and it was a big mistake! The strict timing requirements
> and interfacing caused fits for everyone. SRAM is asynchronous and dead
> easy to use, you will greatly appreciate the simplicity of SRAM in your
> projects."
>
> People privately email me questions along the lines of: "would it be
> possible to port the RISC Oberon system to FPGA board X". I'm BCC'ing
> some in, and suggest they perhaps follow the Oberon mailing list instead
> to understand why it's currently a very difficult question to answer.
> Whilst I would be absolutely delighted to see something viable, "possible"
> is not the same as "easy" or even "sensible".
>
> The point of Project Oberon is not just to make something work, starting
> from scratch, but to make it completely clear and understandable (and
> convincing). The entire book is just that, and amply rewards a careful
> read. I think it's only after you read the whole book through that you
> can really start claiming to understand the philosophy.
>
> F V Tkachov (2014 J. Phys.: Conf. Ser. 523 012011) recently perhaps put it
> even more starkly than Prof. Wirth: the natural tendency towards
> unnecessary complexity creates vulnerability (The Kalashnikov Principle),
> and should be avoided.
>
> Cheers,
> Paul Reed
> http://projectoberon.com
>
>
>
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