[Oberon] RISC5 clock speed and interrupt context switch

[skulski at pas.rochester.edu]

Hello:

  I am exploring the FPGA-based Project Oberon. Two questions popped up
after reading the hardware portion of the new Project Oberon and the NW
Technical Reports from the FPGA-related part of the personal website.

1. The RISC5 clock speed is 25 MHz. Can it be improved to the Microblaze
ballpark that is over 100 MHz?

2. The interrupt HW system. A fast interrupt service can be achieved with
a set of shadow registers for context switching, used on Analog Devices
ADSP21xx series and SHARC. Has this been considered for the RISC5
interrupt system?

I am asking because improving the performance in these two areas could
make RISC5 (or its derivatives) an attractive option for deeply embedded
signal processing.

Regards,
Wojtek