[Oberon] RISC5 versus RISC-V

[skulski at pas.rochester.edu]

Paul:

  there is a potential confusion of what RISC-five really means. Roman
five leads us to UC Berkeley project which is well publicised:
http://riscv.org/

Arabic five leads us to Project Oberon, which is much less known.

There is also an interesting discussion that compares the instructions set
of RISC-V and Epiphany:
http://www.adapteva.com/andreas-blog/analyzing-the-risc-v-instruction-set-architecture/

It seems to me that Epiphany is closer in spirit to N.Wirth thinking than
RISC-V, at least based on the fact that Epiphany's instruction set is
leaner than RISC-V.

Looking at the Adapteva/Parallella project it is a pity that each one of
these many cores of the Parallella board is not running Oberon System
modules. What an interesting project it would have been.

Another (crazy?) idea is to write the Epiphany processor core in VHDL
(avoid verilog, please!) and build a small Epiphany cluster within Zynq
Programmable Logic fabric. Ditto with RISC5. Then compare. These two
architectures must be pretty similar.

An emulated 16-core Epiphany would probably fit within Spartan6-LX150
which has 536 kB BRAM on chip, while 16-core Epiphany has 512 kB (32 kB
per core). One can probably build such a mesh with 16 kB blocks per core.

All these thought knocked to my mind when I was studying the
Adapteva/Parallella website materials for our next project. These papers
were very inspiring to me. Playing with FPGAs along these lines would be
pretty interesting.

Cheers,
Wojtek