[Oberon] Oberon System on the ?

[skulski at pas.rochester.edu]

Bernhard:

thank you for the reference to the Feb/2014 post by Dr. Josef Sedlacek. It
reads very promising:

"In collaboration with the group of prof. Jürg Gutknecht with Dr. Felix
Friedrich and Florian Negele we have developed a system which carries
the registered mark..."

Dr. Felix Friedrich is a moderator of this mailing list. Is he reading
this discussion? If they have something to offer then perhaps they could
tell. The silence is suggestive of saying "no".

Also let me reiterate that my own interest is in a small but efficient
embedded system. It boils down to a question "what comes first, a horse or
a carriage"? Basically, the FPGA-based design can be centered around
either the Programmable Logic (PL), or a Processing System (PS). These
terms are illustrated with the Zynq providing the dual-core hard silicon
ARM (PS) and the attached FPGA to implement the PL part. Zynq chip can be
used to run the Oberon System if it could be compiled for the embedded ARM
cores. (Any volunters to port the compiler?) Lacking the compiler for the
Zynq-ARM, one can do the same trick on a smaller scale using embedded
RISC5, or perhaps MIPS, or whatever.

I am interested in a pretty minimal system to run the PS in an otherwise
PL-dominant design. In principle, the present Wirth system is OK. But it
would help if the V4/S3 legacy could be immediately used, because it is
simply a great and highly useful legacy. So I am asking all these
questions hoping that someone will see the point.

Wojtek