[Oberon] Creating ROM code from Oberon for RISC5

[Gábor Zoltán Sinkó]

I'm trying to Spartan 3e from superimposing the Oberon. Currently, I 
work áthuzalozásán memory. The question you think is my question to the 
previous translation environment to solve your problem, but so far I 
have not gotten to the project.(step by step)

Gabor

On 2015-01-14 21:44, David Hunter wrote:
> Hello all,
>
> First  some background:
> I'm porting the RISC5 processor into a Xilinx Spartan 6 FPGA.   We'd
> like to use the processor as part of our VME instrument module product
> line.   For development, I'm using the Oberon RISC compiler to create
> "ROMable" code (initialized memory) in the FPGA.    Our module is an
> embedded system that does not have a display, keyboard or mouse and
> we're using a different Flash for memory storage. Therefore, I want to
> create different boot load code in the FPGA. I have also put the Oberon
> System on a Spartan 3 evaluation board but just used the ".mcs" file to
> program the FPGA without re-compiling anything.
>
> When I compile using "MODULE*" I get an object file with the special
> start up code that the compiler adds.     Project Oberon Chapter 14
> talks about the process of creating the boot loader and the steps, but
> I'm having trouble finding some of the modules referenced and would like
> more details on how it was done.
>
> So my questions are:
> How is an Oberon RISC object file (.rsc) compiled with "MODULE*"
> converted to a Verilog ".mem" file for loading into the FPGA?
> Was that method used to create the prom.mem file for the Spartan 3
> evaluation board?
> Are there more detailed instructions available on the steps in
> developing a bootloader?
>
> Thanks,
> Dave