[Oberon] Creating ROM code from Oberon for RISC5 (David Hunter)

Thu Jan 15 15:29:31 CET 2015

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Dave:

I hope to hear a detailed answer from Paul who created such files. At
present, the instructions on the Project Oberon web site are missing the
major information. A detailed list of steps would be much appreciated.
http://www.paddedcell.com/projectoberon/RISC-Instructions.txt

I have found some information on pages 10-12 of ds865_microblaze_mcs.pdf
available from the following link:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ds865_microblaze_mcs.pdf

The data flow is diagrammed on page 8. The right side of the diagram shows
the SDK, which in this context is equivalent to Oberon System cross
compiler.

On page 12 they say how to use data2mem from the command line (encircled
in the 3rd frame on that page).

cd project-path
data2mem -p part \
-bm ipcore_dir/component-name_bd.bmm \
-bd /sdk-workspace-path/sdk-program/Debug/sdk-program.elf tag
component-name \
-bt project-name.runs/impl_1/toplevel.bit \
-o b project-name.runs/impl_1/download.bit

It is pretty complicated and most of the MicroBlaze information is
probably not very relevant. It would be really good if paul could provide
a detailed step-by-step description how to generate the .bit file.

Wojtek

> Date: Wed, 14 Jan 2015 15:44:19 -0500
> From: David Hunter <drhunter at frontiernet.net>
> Subject: [Oberon] Creating ROM code from Oberon for RISC5
> To: oberon at lists.inf.ethz.ch
> Message-ID: <54B6D523.80008 at frontiernet.net>
> Content-Type: text/plain; charset=utf-8; format=flowed
>
> Hello all,
>
> First  some background:
> I'm porting the RISC5 processor into a Xilinx Spartan 6 FPGA.   We'd
> like to use the processor as part of our VME instrument module product
> line.   For development, I'm using the Oberon RISC compiler to create
> "ROMable" code (initialized memory) in the FPGA.    Our module is an
> embedded system that does not have a display, keyboard or mouse and
> we're using a different Flash for memory storage. Therefore, I want to
> create different boot load code in the FPGA. I have also put the Oberon
> System on a Spartan 3 evaluation board but just used the ".mcs" file to
> program the FPGA without re-compiling anything.
>
> When I compile using "MODULE*" I get an object file with the special
> start up code that the compiler adds.     Project Oberon Chapter 14
> talks about the process of creating the boot loader and the steps, but
> I'm having trouble finding some of the modules referenced and would like
> more details on how it was done.
>
> So my questions are:
> How is an Oberon RISC object file (.rsc) compiled with "MODULE*"
> converted to a Verilog ".mem" file for loading into the FPGA?
> Was that method used to create the prom.mem file for the Spartan 3
> evaluation board?
> Are there more detailed instructions available on the steps in
> developing a bootloader?
>
> Thanks,
> Dave
>
>
> --
> David Hunter
> Sr. Electrical Engineer
> SkuTek Instrumentation
> 150 Lucius Gordon Dr., Ste 103
> W. Henrietta, NY 14586
> (W) 585-444-7074
> dave at skutek.com
>
>
> ---
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> ------------------------------
>
> Message: 2
> Date: Thu, 15 Jan 2015 10:41:58 +0100
> From: G?bor Zolt?n Sink? <sinkog0208 at gmail.com>
> Subject: Re: [Oberon] Creating ROM code from Oberon for RISC5
> To: oberon at lists.inf.ethz.ch
> Message-ID: <54B78B66.1000801 at gmail.com>
> Content-Type: text/plain; charset=windows-1252; format=flowed
>
> I'm trying to Spartan 3e from superimposing the Oberon. Currently, I
> work ?thuzaloz?s?n memory. The question you think is my question to the
> previous translation environment to solve your problem, but so far I
> have not gotten to the project.(step by step)
>
> Gabor
>
> On 2015-01-14 21:44, David Hunter wrote:
>> Hello all,
>>
>> First  some background:
>> I'm porting the RISC5 processor into a Xilinx Spartan 6 FPGA.   We'd
>> like to use the processor as part of our VME instrument module product
>> line.   For development, I'm using the Oberon RISC compiler to create
>> "ROMable" code (initialized memory) in the FPGA.    Our module is an
>> embedded system that does not have a display, keyboard or mouse and
>> we're using a different Flash for memory storage. Therefore, I want to
>> create different boot load code in the FPGA. I have also put the Oberon
>> System on a Spartan 3 evaluation board but just used the ".mcs" file to
>> program the FPGA without re-compiling anything.
>>
>> When I compile using "MODULE*" I get an object file with the special
>> start up code that the compiler adds.     Project Oberon Chapter 14
>> talks about the process of creating the boot loader and the steps, but
>> I'm having trouble finding some of the modules referenced and would like
>> more details on how it was done.
>>
>> So my questions are:
>> How is an Oberon RISC object file (.rsc) compiled with "MODULE*"
>> converted to a Verilog ".mem" file for loading into the FPGA?
>> Was that method used to create the prom.mem file for the Spartan 3
>> evaluation board?
>> Are there more detailed instructions available on the steps in
>> developing a bootloader?
>>
>> Thanks,
>> Dave
>
>
>
>
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