[Oberon] Spartan 6 Kickstarter project

[Paul Reed]

Dear Mr. Della Casa,

> <http://www.scarabhardware.com/getting-started/>
> (Key specs: Clock Cycle time (min.) 6/7 ns tAC3 Access time from CLK
> (max.)
> 5.4/5.4 ns tRAS Row Active time (min.) 42/49 ns tRC Row Cycle time (min.)
> 60/63 ns)

Prof. Wirth's RISC5 processor design uses a simple asynchronous static RAM
(SRAM) interface with 32-bit word reads and writes occurring in a single
clock cycle.  (Loads and stores therefore take two cycles each, one for
instruction fetch and one for data access - Oberon is designed for a
Von-Neumann style processor.)

This requires the SRAM to be very fast - on the Spartan-3 board, the RAM
is 32 bits wide (two 256Mx16bit chips in parallel) and has an access time
of 10nS.

Sadly, synchronous DRAM (and pseudo-static RAM for that matter) rely on
burst-access to achieve their performance, usually implying a requirement
for a cache and/or an instruction pipeline.  They also usually need to be
initialised and in the case of DDR, continuously calibrated; all this
necessitates a much more complex hardware interface.  This added
complexity is considerably against the objectives of the RISC-based
Project Oberon design.

A nice small FPGA board with some 32-bit wide fast SRAM would indeed be a
worthwhile Kickstarter project, because it would be genuinely useful in
helping more people design with FPGAs due to the reduced complexity wall.

Hope that helps,
Paul