[Oberon] HDMI and SD interfaces

[Jörg Straube]

Wojtek

Indeed, the pipistrello board provides a Spartan-6 LX45 in a BGA package.
Project Oberon uses a pixel clock of 75 MHz resulting in one HDMI TMDS channel running at 750 Mbps.

Verilog
- - - - - -
dvi dvi_blk(
  .reset(~rst),
  .pll_locked(pll_locked),
  .clkx1in(pclk),         // 75 MHz
  .clkx2in(pclkx2),     // 150 MHz
  .clkx10in(pllclk0),   // 750 MHz
  .blue_in( {8{RGB[0]}} ),
  .green_in( {8{RGB[1]}} ),
  .red_in( {8{RGB[2]}} ),
  .hsync(hsync),
  .vsync(vsync),
  .vde(vde),
  .TMDS(TMDS),
  .TMDSB(TMDSB)
);

Jörg

> Am 13.05.2015 um 17:44 schrieb skulski at pas.rochester.edu:
> 
> Hello:
> 
> A few remarks from the hardware standpoint:
> 
>> SD Cards are quite simple to handle. In principle its a stupid serial
>> Flash with a SPI interface.
> 
> SPI is the lowest speed interface to SD. The SD standard uses up to four
> bit lines. It would be nice to use four data lines instead of just one.
> The operation would be faster. IP cores exist for doing so.
> 
>>> Is HDMI complex?
> [snip
>> But in principle its a FIFO, a serializer and a TMDS coder (the most
>> complex part).
> 
> HDMI output is high speed. I doubt it can run in the low cost quad flat
> pack FPGAs because the lead inductance will not permit speeds higher than
> about 200 Mbps. You need a BGA package to run at higher bit rates required
> by the HDMI. It means that the board assembly will be a bit more expensive
> due to the BGA pick-and-place requirements. Board layout must be careful
> to provide good signal integrity.
> 
> The serializer-deserializer used in HDMI designs need be tailored to the
> specific FPGAs. I doubt one can design a generic HDMI serdes that would
> run across the chip spectrum. Just to give you an example, it took us
> several months to develop a robust receiver of multi-lane LVDS signals
> approaching the FPGA limit. It was somewat similar to HDMI, but in
> reverse. The bottom line: use the IP which is available and tested, such
> as the one available from Hamsterworks. Do not try the "as simple as
> possible" approach. Everything seems simple if you stay around 10% of the
> max nominal clock rate. Nothing is simple when you approach the hardware
> speed limits, which HDMI is doing.
> 
> Wojtek
> 
> 
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

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