[Oberon] New FPGA Oberon board

Douglas G. Danforth danforth at greenwoodfarm.com
Tue May 19 10:56:29 CEST 2015


Timing?   dt = wirelength/c

On 5/19/2015 12:08 AM, Bill Buzzell wrote:
>  It appears that we should be able to simply stretch out some more 
> board real estate/space (in the EagleCad project), route these 
> untapped 14 pins how/where we desire them, we have plenty of I/O's now. 




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