[Oberon] FPGA-related Project Oberon Customizations

[Joerg]

Thanx. This slipped my eyes :-(
Jörg
> Am 16.02.2016 um 22:29 schrieb Chris Burrows <chris at cfbsoftware.com>:
> 
>> -----Original Message-----
>> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
>> Jörg
>> Sent: Tuesday, 16 February 2016 8:30 PM
>> To: 'ETH Oberon and related systems'
>> Subject: Re: [Oberon] FPGA-related Project Oberon Customizations
>> 
>> Hi
>> 
>> One idea to adopt the RISC5 to a RISC6 is to enlarge the addressable
>> memory from 1MB to 2MB.
> 
> Better than this (i.e. 16MB) is already possible for RISC5. This has been
> available since last September as announced in the Oberon News:
> 
>  "Address bus width changed from 20 to 24"
> 
> https://www.inf.ethz.ch/personal/wirth/news.txt
> 
> Regards,
> Chris
> 
> Chris Burrows
> CFB Software
> http://www.astrobe.com
> 
> 
> 
> 
> 
> 
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